公开(公告)号：US10043027B1

公开(公告)日：2018-08-07

申请号：US14946607

申请日：2015-11-19

Applicant: Xilinx, Inc.

Inventor： Gangadhar Budde ,  Pradeep Kumar Mishra ,  Somdutt Javre

IPC: G06F17/50 ,  G06F21/62 ,  G06F3/06

Abstract: Methods and systems are disclosed for determining mask-value pairs for controlling access to a memory segment for a plurality of IDs. A first set of mask-value pairs is determined for a set of allowed identifiers (IDs) and a set of non-allowed IDs. Each mask-value pair of the first set matches at least one ID of the set of allowed IDs and does not match any of the IDs of the set of non-allowed IDs. Redundant mask-value pairs are removed from the first set to produce a second set. Subsets of mask-value pairs in the second set that match the entire set of allowed IDs are determined. The subset having the highest processing efficiency is determined and selected. A set of configuration data is generated that is configured to cause a memory management circuit to enforce access to the memory segment based on the selected subset of mask-value pairs.

公开(公告)号：US09589088B1

公开(公告)日：2017-03-07

申请号：US14746646

申请日：2015-06-22

Applicant: Xilinx, Inc.

Inventor： Pradeep Kumar Mishra ,  Gangadhar Budde ,  Somdutt Javre ,  Siddharth Rele

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by the user-defined permissions. A first portion of configuration data is generated that is configured to cause a memory management circuit in the programmable IC to enforce access to address ranges, corresponding to the respective memory segments, in a memory of the programmable IC according to the respective access control entries. A second portion of configuration data is generated that is configured to cause programmable resources of the programmable IC to implement the circuit design.

Abstract translation: 各种示例性实现涉及用于分配用于可编程IC中的电路设计的存储器的电路和方法。 提供用户接口来定义子系统，主电路，存储器段和由主电路访问存储器段的许可。 对于每个定义的存储器段，生成相应的访问控制条目，其包括用于通过用户定义的许可来确定允许访问存储器段的主电路的数据。 生成配置数据的第一部分，其被配置为使得可编程IC中的存储器管理电路根据相应的访问控制条目强制对可编程IC的存储器中对应于相应存储器段的地址范围的访问。 生成配置数据的第二部分，其被配置为使得可编程IC的可编程资源实现电路设计。

公开(公告)号：US09543934B1

公开(公告)日：2017-01-10

申请号：US14682758

申请日：2015-04-09

Applicant: Xilinx, Inc.

Inventor： Somdutt Javre ,  Pradeep Kumar Mishra ,  Gangadhar Budde ,  Siddharth Rele

IPC: G06F1/10 ,  H03K5/00 ,  H03L7/18 ,  G06F1/08 ,  G06F1/04 ,  G06F1/06

CPC classification number: H03K5/00006 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03L7/18

Abstract: In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.

Abstract translation: 在用于确定时钟网络中用于编程倍频器和分频器电路的乘数值和除数值的方法中，使用相对于多个时钟控制电路块的所请求的频率值的相应的请求频率值和相应的公差电平。 生成多个解集，其中每个解集合包括乘数值和相关的除数值，使得所得到的实际频率满足相应的公差电平。 针对多个解集合确定各组时钟误差值，每个时钟误差值对应于时钟电路块。 根据相应的计时误差值集合确定解集合误差值，并且选择并存储具有最小解集合误差值的解集。

公开(公告)号：US09436785B1

公开(公告)日：2016-09-06

申请号：US14491656

申请日：2014-09-19

Applicant: Xilinx, Inc.

Inventor： Somdutt Javre ,  Pradeep Kumar Mishra ,  Siddharth Rele

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2213/0038

Abstract: Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.

Abstract translation: 片上系统（SOC）的分层预设和规则库配置包括接收用户输入，选择用于启用的SOC的第一电路块，并使用处理器确定根据用户输入的第一顶级预设 第一电路块。 从第一电路块的多个分层有序的预设确定所选择的中间预设。 根据第一电路块的所选择的中间预置，自动地为第一电路块确定低电平预设。 例如，通过将它们加载到SOC中来输出低电平预设。