公开(公告)号：US20210150072A1

公开(公告)日：2021-05-20

申请号：US16686070

申请日：2019-11-15

Applicant: XILINX, INC.

Inventor： Gangadhar Budde ,  Shreegopal S. Agrawal ,  Siddharth Rele ,  Subhojit Deb

IPC: G06F21/76

Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.

公开(公告)号：US20220035607A1

公开(公告)日：2022-02-03

申请号：US17500509

申请日：2021-10-13

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

公开(公告)号：US11029964B1

公开(公告)日：2021-06-08

申请号：US16282216

申请日：2019-02-21

Applicant: Xilinx, Inc.

Inventor： Siddharth Rele ,  Shreegopal S. Agrawal ,  Kaustuv Manji ,  Aditya Chaubal

IPC: G06F9/4401 ,  G06F21/30 ,  G06F15/78

Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.

公开(公告)号：US10853134B2

公开(公告)日：2020-12-01

申请号：US15956480

申请日：2018-04-18

Applicant: Xilinx, Inc.

Inventor： Somdutt Javre ,  Siddharth Rele ,  Gangadhar Budde ,  Appa Rao Nali ,  Chaitanya Kamarapu

IPC: G06F9/50 ,  G06F8/20 ,  G06F9/4401 ,  G06F8/30

Abstract: Multi-domain creation and isolation within a heterogeneous System-on-Chip (SoC) may include receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous SoC and creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources. The method may include assigning, using the computer hardware, an operating system to each domain and generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

公开(公告)号：US10713403B1

公开(公告)日：2020-07-14

申请号：US16374494

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Shreegopal S. Agrawal ,  Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Benjamin D. Curry ,  Siddharth Rele ,  Sozon Panou

IPC: G06F30/30 ,  G06F30/20 ,  G06F30/31 ,  G06F30/327 ,  G06F30/323

Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.

公开(公告)号：US11645053B2

公开(公告)日：2023-05-09

申请号：US17500509

申请日：2021-10-13

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

CPC classification number: G06F8/41 ,  G06F8/447 ,  H03K19/17724

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

公开(公告)号：US11188312B2

公开(公告)日：2021-11-30

申请号：US16421444

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US09589088B1

公开(公告)日：2017-03-07

申请号：US14746646

申请日：2015-06-22

Applicant: Xilinx, Inc.

Inventor： Pradeep Kumar Mishra ,  Gangadhar Budde ,  Somdutt Javre ,  Siddharth Rele

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by the user-defined permissions. A first portion of configuration data is generated that is configured to cause a memory management circuit in the programmable IC to enforce access to address ranges, corresponding to the respective memory segments, in a memory of the programmable IC according to the respective access control entries. A second portion of configuration data is generated that is configured to cause programmable resources of the programmable IC to implement the circuit design.

Abstract translation: 各种示例性实现涉及用于分配用于可编程IC中的电路设计的存储器的电路和方法。 提供用户接口来定义子系统，主电路，存储器段和由主电路访问存储器段的许可。 对于每个定义的存储器段，生成相应的访问控制条目，其包括用于通过用户定义的许可来确定允许访问存储器段的主电路的数据。 生成配置数据的第一部分，其被配置为使得可编程IC中的存储器管理电路根据相应的访问控制条目强制对可编程IC的存储器中对应于相应存储器段的地址范围的访问。 生成配置数据的第二部分，其被配置为使得可编程IC的可编程资源实现电路设计。

公开(公告)号：US09543934B1

公开(公告)日：2017-01-10

申请号：US14682758

申请日：2015-04-09

Applicant: Xilinx, Inc.

Inventor： Somdutt Javre ,  Pradeep Kumar Mishra ,  Gangadhar Budde ,  Siddharth Rele

IPC: G06F1/10 ,  H03K5/00 ,  H03L7/18 ,  G06F1/08 ,  G06F1/04 ,  G06F1/06

CPC classification number: H03K5/00006 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03L7/18

Abstract: In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.

Abstract translation: 在用于确定时钟网络中用于编程倍频器和分频器电路的乘数值和除数值的方法中，使用相对于多个时钟控制电路块的所请求的频率值的相应的请求频率值和相应的公差电平。 生成多个解集，其中每个解集合包括乘数值和相关的除数值，使得所得到的实际频率满足相应的公差电平。 针对多个解集合确定各组时钟误差值，每个时钟误差值对应于时钟电路块。 根据相应的计时误差值集合确定解集合误差值，并且选择并存储具有最小解集合误差值的解集。

公开(公告)号：US09436785B1

公开(公告)日：2016-09-06

申请号：US14491656

申请日：2014-09-19

Applicant: Xilinx, Inc.

Inventor： Somdutt Javre ,  Pradeep Kumar Mishra ,  Siddharth Rele

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2213/0038

Abstract: Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.

Abstract translation: 片上系统（SOC）的分层预设和规则库配置包括接收用户输入，选择用于启用的SOC的第一电路块，并使用处理器确定根据用户输入的第一顶级预设 第一电路块。 从第一电路块的多个分层有序的预设确定所选择的中间预设。 根据第一电路块的所选择的中间预置，自动地为第一电路块确定低电平预设。 例如，通过将它们加载到SOC中来输出低电平预设。