公开(公告)号：US11831743B1

公开(公告)日：2023-11-28

申请号：US16242860

申请日：2019-01-08

Applicant: Xilinx, Inc.

Inventor： Jaime Herrera ,  Gordon J. Brebner ,  Ian McBryan ,  Rowan Lyons

IPC: H04L69/22 ,  H04L69/324

CPC classification number: H04L69/22 ,  H04L69/324

Abstract: Apparatus and associated methods relate to packet header field extraction as defined by a high level language and implemented in a minimum number of hardware streaming parsing stages to speculatively extract header fields from among multiple possible header sequences. In an illustrative example, the number of stages may be determined from the longest possible header sequence in any received packet. For each possible header sequence, one or more headers may be assigned to each stage, for example, based on a parse graph. Each pipelined stage may resolve a correct header sequence, for example, by sequentially extracting length and transition information from an adjacent prior stage to determine offset of the next header. By speculatively extracting selected fields from every possible position in each pipeline stage, a correct value may be selected using sequential hardware streaming pipelines to substantially reduce parsing latency.

公开(公告)号：US10834241B1

公开(公告)日：2020-11-10

申请号：US16242876

申请日：2019-01-08

Applicant: Xilinx, Inc.

Inventor： Ian McBryan ,  Gordon J. Brebner ,  Jaime Herrera ,  Rowan Lyons

IPC: H04J3/24 ,  H04L29/06 ,  H04L12/723

Abstract: Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.

公开(公告)号：US11425036B1

公开(公告)日：2022-08-23

申请号：US16386127

申请日：2019-04-16

Applicant: Xilinx, Inc.

Inventor： Jaime Herrera ,  Gordon J. Brebner ,  Ian McBryan ,  Rowan Lyons

IPC: H04L45/74 ,  H04L69/22 ,  H04L47/56 ,  H04L45/24

Abstract: A match-action circuit includes one or more conditional logic circuits, each having an input coupled to input header or metadata of a network packet, and each configured to generate an enable signal as a function of one or more signals of the header or metadata. Each match circuit of one or more match circuits is configured with response values associated with key values. Each match circuit is configured to conditionally lookup response value(s) associated with an input key value from the header or metadata in response to the enable signal from a conditional logic circuit. One or more action circuits are configured to conditionally modify, in response to states of the response value(s) output from the match circuit(s), data of the header or the metadata.

公开(公告)号：US11144235B1

公开(公告)日：2021-10-12

申请号：US16534527

申请日：2019-08-07

Applicant: Xilinx, Inc.

Inventor： Rowan Lyons ,  Noel Brady

IPC: G06F3/06 ,  G06F11/26

Abstract: Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.