公开(公告)号：US10891414B2

公开(公告)日：2021-01-12

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F30/34

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US20200371759A1

公开(公告)日：2020-11-26

申请号：US16421444

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F8/41 ,  H03K19/177

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US20200372123A1

公开(公告)日：2020-11-26

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F17/50

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.