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    System and method for import and export of design constraints
    1.
    发明授权
    System and method for import and export of design constraints 有权
    导入和导出设计约束的系统和方法

    公开(公告)号：US08612916B1

    公开(公告)日：2013-12-17

    申请号：US13709733

    申请日：2012-12-10

    Applicant: Xilinx, Inc.

    Inventor： Brendan M. O'Higgins ,  Pradip K. Jha ,  Dinesh K. Monga ,  David A. Knol

    IPC: G06F17/50

    CPC classification number: G06F17/5054

    Abstract: A method is provided for exporting design constraints from a circuit design. In response to a first user command indicating a design constraint and a pattern, the design constraint is assigned to each object in the circuit design that matches the pattern, and the pattern is stored in a database. In response to a second user command to export design constraints of the circuit design, for each design constraint assigned to a respective set of objects of the circuit design, a pattern stored in the database that matches the respective set of the objects is determined and the design constraint is added to an export file in a format that uses the determined pattern. Design constraints on individual ones of the set of the objects indicated by the determined pattern are omitted from the export file.

    Abstract translation: 提供了一种从电路设计中输出设计约束的方法。 响应于指示设计约束和模式的第一用户命令，将设计约束分配给与模式匹配的电路设计中的每个对象，并且将模式存储在数据库中。 响应于第二用户命令导出电路设计的设计约束，对于分配给电路设计的相应对象集合的每个设计约束，确定存储在数据库中与对象的相应集合匹配的模式，并且 设计约束以使用确定的模式的格式添加到导出文件。 导出文件中省略了由确定的图案指示的对象集中的各个对象的设计约束。

    Constraints for applications in a heterogeneous programming environment
    2.
    发明授权
    Constraints for applications in a heterogeneous programming environment 有权

    公开(公告)号：US11113030B1

    公开(公告)日：2021-09-07

    申请号：US16420905

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Dinesh K. Monga ,  Shail Aditya Gupta ,  Samuel R. Bayliss ,  Kaushik Barman

    IPC: G06F9/44 ,  G06F8/10 ,  G06F8/34 ,  G06F8/41

    Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.

    Unified data model for heterogeneous integrated circuit
    4.
    发明授权
    Unified data model for heterogeneous integrated circuit 有权

    公开(公告)号：US11176296B1

    公开(公告)日：2021-11-16

    申请号：US17007177

    申请日：2020-08-31

    Applicant: Xilinx, Inc.

    Inventor： Pradip Jha ,  Brendan Matthew O'Higgins ,  Dinesh K. Monga ,  Bart Reynolds ,  Ryan Linderman

    IPC: G06F30/30 ,  G06F30/327 ,  G06F30/33 ,  G06F9/451 ,  G06F15/78 ,  G06F30/39

    Abstract: A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.

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