公开(公告)号：US10565346B1

公开(公告)日：2020-02-18

申请号：US15640009

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Vishal Suthar ,  Dinesh D. Gaitonde ,  Amit Gupta ,  Jinny Singh

IPC: G06F17/50

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.

公开(公告)号：US10891414B2

公开(公告)日：2021-01-12

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F30/34

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US20200372123A1

公开(公告)日：2020-11-26

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F17/50

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.