公开(公告)号：US20240202423A1

公开(公告)日：2024-06-20

申请号：US18066231

申请日：2022-12-14

Applicant: Xilinx, Inc.

Inventor： Dinesh D. Gaitonde ,  Chirag Ravishankar ,  Stefan Nikolic

IPC: G06F30/3947

CPC classification number: G06F30/3947

Abstract: Multi-stage routing for a circuit design includes performing, using computer hardware, a global routing of the circuit design using a hybrid routing graph for a target integrated circuit. The hybrid routing graph includes routing nodes and a plurality of coarsened routing nodes. Each coarsened routing node includes a plurality of constituent routing nodes that are treated as a single node during the global routing. A detailed routing of the circuit design is performed using the computer hardware to generate a legal routing solution for the circuit design. The detailed routing is performed by routing, in parallel, the nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.