公开(公告)号：US20230318921A1

公开(公告)日：2023-10-05

申请号：US17657977

申请日：2022-04-05

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Dinesh D. Gaitonde

IPC: H04L41/0893 ,  H04L49/109 ,  H04J3/02

CPC classification number: H04L41/0893 ,  H04J3/02 ,  H04L49/109

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

公开(公告)号：US10565346B1

公开(公告)日：2020-02-18

申请号：US15640009

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Vishal Suthar ,  Dinesh D. Gaitonde ,  Amit Gupta ,  Jinny Singh

IPC: G06F17/50

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.

公开(公告)号：US20200026684A1

公开(公告)日：2020-01-23

申请号：US16041473

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Sagheer Ahmad ,  Ygal Arbel ,  Dinesh D. Gaitonde

IPC: G06F15/78 ,  H04L12/24 ,  H04L12/933

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

公开(公告)号：US11720255B1

公开(公告)日：2023-08-08

申请号：US17184458

申请日：2021-02-24

Applicant: XILINX, INC.

Inventor： Abhishek Kumar Jain ,  Henri Fraisse ,  Dinesh D. Gaitonde

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

公开(公告)号：US11681846B1

公开(公告)日：2023-06-20

申请号：US17147163

申请日：2021-01-12

Applicant: XILINX, INC.

Inventor： Xiaojian Yang ,  Frederic Revenu ,  Dinesh D. Gaitonde ,  Amit Gupta

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

公开(公告)号：US08972920B1

公开(公告)日：2015-03-03

申请号：US14178035

申请日：2014-02-11

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Dinesh D. Gaitonde ,  Yau-Tsun S. Li

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5031 ,  G06F17/5054 ,  G06F2217/84

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract translation: 重新预算连接包括检测用于电路设计的预算事件，并且响应于检测到预算事件，使用处理器计算电路设计的所选择的组合电路元件的增量，使用输入的松弛和输出的松弛 选择的组合电路元件。 使用处理器，使用响应于检测预算事件的增量来调整所选择的组合电路元件的连接的延迟预算。

公开(公告)号：US12079484B2

公开(公告)日：2024-09-03

申请号：US18230117

申请日：2023-08-03

Applicant: XILINX, INC.

Inventor： Abhishek Kumar Jain ,  Henri Fraisse ,  Dinesh D. Gaitonde

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

公开(公告)号：US20240202423A1

公开(公告)日：2024-06-20

申请号：US18066231

申请日：2022-12-14

Applicant: Xilinx, Inc.

Inventor： Dinesh D. Gaitonde ,  Chirag Ravishankar ,  Stefan Nikolic

IPC: G06F30/3947

CPC classification number: G06F30/3947

Abstract: Multi-stage routing for a circuit design includes performing, using computer hardware, a global routing of the circuit design using a hybrid routing graph for a target integrated circuit. The hybrid routing graph includes routing nodes and a plurality of coarsened routing nodes. Each coarsened routing node includes a plurality of constituent routing nodes that are treated as a single node during the global routing. A detailed routing of the circuit design is performed using the computer hardware to generate a legal routing solution for the circuit design. The detailed routing is performed by routing, in parallel, the nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.

公开(公告)号：US11888693B2

公开(公告)日：2024-01-30

申请号：US17657977

申请日：2022-04-05

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Dinesh D. Gaitonde

IPC: H04J3/02 ,  H04L41/08 ,  H04L49/10 ,  H04L41/0893 ,  H04L49/109

CPC classification number: H04L41/0893 ,  H04J3/02 ,  H04L49/109

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

公开(公告)号：US10747929B1

公开(公告)日：2020-08-18

申请号：US16255496

申请日：2019-01-23

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse ,  Dinesh D. Gaitonde ,  Chirag Ravishankar

IPC: G06F30/30 ,  G06F30/36 ,  G06F30/398 ,  G06F119/12

Abstract: A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.