公开(公告)号：US20230318921A1

公开(公告)日：2023-10-05

申请号：US17657977

申请日：2022-04-05

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Dinesh D. Gaitonde

IPC: H04L41/0893 ,  H04L49/109 ,  H04J3/02

CPC classification number: H04L41/0893 ,  H04J3/02 ,  H04L49/109

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

公开(公告)号：US10810341B1

公开(公告)日：2020-10-20

申请号：US16443244

申请日：2019-06-17

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Davis Moore

IPC: G06F30/30 ,  G06F30/394 ,  G06F111/04

Abstract: Circuit pin constraints input to a design tool specify respective sets of circuit pins belonging to circuit blocks, and input interface pin constraints specify respective sets of interface pins belonging to instances of an interface circuit. The design tool generates pin solutions, and each pin solution includes pin assignments of the circuit pins to the interface pins. The design tool applies an objective function to the pin solutions and selects one pin solution that satisfies the objective function. The design tool then specifies in a circuit design, connections between the circuit pins and the interface pins according to the selected pin solution.

公开(公告)号：US20240202423A1

公开(公告)日：2024-06-20

申请号：US18066231

申请日：2022-12-14

Applicant: Xilinx, Inc.

Inventor： Dinesh D. Gaitonde ,  Chirag Ravishankar ,  Stefan Nikolic

IPC: G06F30/3947

CPC classification number: G06F30/3947

Abstract: Multi-stage routing for a circuit design includes performing, using computer hardware, a global routing of the circuit design using a hybrid routing graph for a target integrated circuit. The hybrid routing graph includes routing nodes and a plurality of coarsened routing nodes. Each coarsened routing node includes a plurality of constituent routing nodes that are treated as a single node during the global routing. A detailed routing of the circuit design is performed using the computer hardware to generate a legal routing solution for the circuit design. The detailed routing is performed by routing, in parallel, the nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.

公开(公告)号：US11888693B2

公开(公告)日：2024-01-30

申请号：US17657977

申请日：2022-04-05

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Dinesh D. Gaitonde

IPC: H04J3/02 ,  H04L41/08 ,  H04L49/10 ,  H04L41/0893 ,  H04L49/109

CPC classification number: H04L41/0893 ,  H04J3/02 ,  H04L49/109

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

公开(公告)号：US10747929B1

公开(公告)日：2020-08-18

申请号：US16255496

申请日：2019-01-23

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse ,  Dinesh D. Gaitonde ,  Chirag Ravishankar

IPC: G06F30/30 ,  G06F30/36 ,  G06F30/398 ,  G06F119/12

Abstract: A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.

公开(公告)号：US10715149B1

公开(公告)日：2020-07-14

申请号：US16513190

申请日：2019-07-16

Applicant: Xilinx, Inc.

Inventor： Eric F. Dellinger ,  Jay T. Young ,  Brian C. Gaide ,  Chirag Ravishankar ,  Davis Moore ,  Steven P. Young

IPC: H03K19/17736 ,  H03K19/17724

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.