公开(公告)号：US10534729B1

公开(公告)日：2020-01-14

申请号：US15979044

申请日：2018-05-14

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee ,  Theepan Moorthy

IPC: G06F13/00 ,  G06F13/16 ,  G06F1/04 ,  G06F13/42

Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.