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公开(公告)号：US20120120749A1
公开(公告)日：2012-05-17
申请号：US13358442
申请日：2012-01-25
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
摘要翻译： 包含存储器的集成电路包括IEEE 1149.1（JTAG）控制的自修复系统，其允许在集成电路被封装之后永久地修复存储器。 JTAG控制的自修复系统允许用户使用外部提供的电压来引导电路熔断熔断器，以电耦合或隔离组件，以使用JTAG标准TMS和TCK信号永久修复存储器位置。 系统可以可选地使用修复定序器顺序修复多于一个的存储器位置。
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2.发明授权Systems and methods for defect testing of externally accessible integrated circuit interconnects 失效外部可访问的集成电路互连的缺陷测试系统和方法公开(公告)号：US07612574B2
公开(公告)日：2009-11-03
申请号：US11627108
申请日：2007-01-25
CPC分类号： G01R31/31715 , G01R31/3004 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/56 , G11C2029/5006
摘要： Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
摘要翻译： 装置和方法在集成电路中提供内置的测试增强功能。 这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。 所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。 在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。 这允许测试焊盘和输入缓冲器之间的连续性。 输出缓冲区也可以根据需要进行测试。 在另一个实施例中，管芯的两个或更多焊盘电耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。
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公开(公告)号：US08230274B2
公开(公告)日：2012-07-24
申请号：US13358442
申请日：2012-01-25
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
摘要翻译： 包含存储器的集成电路包括IEEE 1149.1（JTAG）控制的自修复系统，其允许在集成电路被封装之后永久地修复存储器。 JTAG控制的自修复系统允许用户使用外部提供的电压来引导电路熔断熔断器，以电耦合或隔离组件，以使用JTAG标准TMS和TCK信号永久修复存储器位置。 系统可以可选地使用修复定序器顺序修复多于一个的存储器位置。
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4.发明申请SYSTEMS AND METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS 失效外部可访问集成电路互连的缺陷测试系统与方法公开(公告)号：US20080180116A1
公开(公告)日：2008-07-31
申请号：US11627108
申请日：2007-01-25
IPC分类号： G01R31/02
CPC分类号： G01R31/31715 , G01R31/3004 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/56 , G11C2029/5006
摘要： Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
摘要翻译： 装置和方法在集成电路中提供内置的测试增强功能。 这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。 所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。 在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。 这允许测试焊盘和输入缓冲器之间的连续性。 输出缓冲区也可以根据需要进行测试。 在另一个实施例中，管芯的两个或更多焊盘电耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。
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公开(公告)号：US20110035635A1
公开(公告)日：2011-02-10
申请号：US12906764
申请日：2010-10-18
IPC分类号： G06F11/20
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
摘要翻译： 包含存储器的集成电路包括IEEE 1149.1（JTAG）控制的自修复系统，其允许在集成电路被封装之后永久地修复存储器。 JTAG控制的自修复系统允许用户使用外部提供的电压来引导电路熔断熔断器，以电耦合或隔离组件，以使用JTAG标准TMS和TCK信号永久修复存储器位置。 系统可以可选地使用修复定序器顺序修复多于一个的存储器位置。
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公开(公告)号：US07721163B2
公开(公告)日：2010-05-18
申请号：US11789367
申请日：2007-04-23
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
摘要翻译： 包含存储器的集成电路包括IEEE 1149.1（JTAG）控制的自修复系统，其允许在集成电路被封装之后永久地修复存储器。 JTAG控制的自修复系统允许用户使用外部提供的电压来引导电路熔断熔断器，以电耦合或隔离组件，以使用JTAG标准TMS和TCK信号永久修复存储器位置。 系统可以可选地使用修复定序器顺序修复多于一个的存储器位置。
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公开(公告)号：US08122304B2
公开(公告)日：2012-02-21
申请号：US12906764
申请日：2010-10-18
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
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8.发明申请METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS 有权外部可访问集成电路互连的缺陷测试方法公开(公告)号：US20110273185A1
公开(公告)日：2011-11-10
申请号：US13183931
申请日：2011-07-15
IPC分类号： G01R31/04
CPC分类号： G01R31/31715 , G01R31/3004 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/56 , G11C2029/5006
摘要： Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
摘要翻译： 装置和方法在集成电路中提供内置的测试增强功能。 这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。 所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。 在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。 这允许测试焊盘和输入缓冲器之间的连续性。 输出缓冲区也可以根据需要进行测试。 在另一个实施例中，管芯的两个或更多个焊盘电子耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。
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9.发明授权Systems and methods for defect testing of externally accessible integrated circuit interconnects 有权外部可访问的集成电路互连的缺陷测试系统和方法公开(公告)号：US07990163B2
公开(公告)日：2011-08-02
申请号：US12570138
申请日：2009-09-30
IPC分类号： G01R31/02
CPC分类号： G01R31/31715 , G01R31/3004 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/56 , G11C2029/5006
摘要： Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
摘要翻译： 装置和方法在集成电路中提供内置的测试增强功能。 这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。 所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。 在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。 这允许测试焊盘和输入缓冲器之间的连续性。 输出缓冲区也可以根据需要进行测试。 在另一个实施例中，管芯的两个或更多焊盘电耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。
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公开(公告)号：US07831870B2
公开(公告)日：2010-11-09
申请号：US12764810
申请日：2010-04-21
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
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