公开(公告)号：US20120049267A1

公开(公告)日：2012-03-01

申请号：US13218971

申请日：2011-08-26

申请人： Young Kyun JUNG

发明人： Young Kyun JUNG

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.

摘要翻译： 半导体器件包括形成在衬底上的管道沟道层，形成在管道沟道层上以将管道沟道层耦合到位线的第一垂直沟道层，在管道沟道层上形成的第二垂直沟道层，以耦合管道 沟道层到源极线，多层，包括电荷陷阱层并形成为围绕第一垂直沟道层，第二垂直沟道层和管道沟道层，形成为围绕多层的绝缘势垒层， 形成在管道沟道层和位线之间的多个第一导电层，其中第一垂直沟道层穿过第一导电层，以及形成在管道沟道层和源极线之间的多个第二导电层，其中， 第二垂直层通过第二导电层。

公开(公告)号：US20130043521A1

公开(公告)日：2013-02-21

申请号：US13585336

申请日：2012-08-14

申请人： Young Kyun JUNG

发明人： Young Kyun JUNG

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L27/11556 ,  H01L29/7889

摘要： A method of manufacturing a 3-Dimensional (3-D) non-volatile memory device includes forming first material layers and second material layers alternately, forming at least one first trench by etching the first material layers and the second material layers, forming floating gate regions by recessing the second material layers, exposed to the first trench, forming a first charge blocking layer on surfaces of the first trench and the floating gate regions, forming a first conductive layer on the first charge blocking layer, etching the first conductive layer on the upper side of the first trench, forming a second charge blocking layer on the first charge blocking layer exposed by etching the first conductive layer, and forming floating gates in the respective floating gate regions by etching the first conductive layer.

摘要翻译： 制造三维（3-D）非易失性存储器件的方法包括交替地形成第一材料层和第二材料层，通过蚀刻第一材料层和第二材料层形成至少一个第一沟槽，形成浮动栅极 区域，通过使暴露于第一沟槽的第二材料层凹陷，在第一沟槽和浮动栅极区域的表面上形成第一电荷阻挡层，在第一电荷阻挡层上形成第一导电层， 在所述第一沟槽的上侧，通过蚀刻所述第一导电层而在所述第一电荷阻挡层上形成第二电荷阻挡层，以及通过蚀刻所述第一导电层在所述浮置栅极区域中形成浮置栅极。