DATA RETRANSMISSION DECODING METHOD, APPARATUS AND SYSTEM, AND COMMUNICATION DEVICE

    公开(公告)号:US20220069946A1

    公开(公告)日:2022-03-03

    申请号:US17418773

    申请日:2019-09-27

    Abstract: Disclosed are a data retransmission decoding method, apparatus and system, and a communication device. The method includes: obtaining retransmitted data to be decoded, the retransmitted data to be decoded including a code block to be decoded (S102); according to stored check state information of a previously decoded code block, judging whether the code block to be decoded includes a target code block required to be decoded again (S104); and if the code block to be decoded includes the target code block required to be decoded again, merging and decoding a currently stored first code block and the target code block based on a predetermined decoding parameter (S106), wherein the first code block is a code block corresponding to the target code block.

    TIME SYNCHRONIZATION METHOD AND APPARATUS FOR NETWORK DEVICES AND TIME SYNCHRONIZATION SERVER

    公开(公告)号:US20170272190A1

    公开(公告)日:2017-09-21

    申请号:US15328911

    申请日:2014-12-23

    CPC classification number: H04J3/0658 H04J3/0667

    Abstract: A time synchronization method and apparatus for network devices and a time synchronization server are disclosed, which relates to the field of communication technology, to solve the problem of failing to perform high-capacity and centralized time synchronization due to less timely processing of a time synchronization message in the related art. The method includes: a programmable logic device receiving and parsing a time synchronization message from a to-be-synchronized device in a physical layer, wherein the time synchronization message carries a synchronization parameter; the programmable logic device generating a reply message for the time synchronization message according to local reference time and update configurations of the synchronization parameter; and the programmable logic device sending the reply message and a link establishment and communication message from a CPU to the to-be-synchronized device in a preset order.

    Method and Device for Receiving and Sending Message, Channel Unit and Communication Equipment

    公开(公告)号:US20170222915A1

    公开(公告)日:2017-08-03

    申请号:US15328285

    申请日:2014-12-12

    CPC classification number: H04L45/125 H04L12/6418 H04L49/20 H04L69/324

    Abstract: The present disclosure discloses a method and device for receiving and sending a message, a channel unit and communication equipment. The method for receiving and sending the message of the present disclosure specifically includes that: a channel unit receives a message sent by equipment born by an equipment network interface; the channel unit judges whether the received message is a message required to be processed by a CPU or not; when a judgment result is that the received message is the message required to be processed by the CPU, the channel unit sends the message to the CPU, receives a response message returned by the CPU, and directly forwards the response message to the equipment; and when the judgment result is that the received message is not the message required to be processed by the CPU, the channel unit generates and sends a corresponding response message to the equipment.

    Clock Synchronization Method and Apparatus

    公开(公告)号:US20170195076A1

    公开(公告)日:2017-07-06

    申请号:US15321736

    申请日:2014-11-03

    CPC classification number: H04J3/0697 G06F1/12 G06F1/14 G06F9/4881 H04J3/0667

    Abstract: The present disclosure provides a clock synchronization method and a clock synchronization apparatus. Herein the method includes: a physical layer device acquires a synchronization message used for a device to be synchronized to implement clock synchronization; and the physical side device transmits the synchronization message to the device to be synchronized. By means of the abovementioned technical solution provided by the present disclosure, the problems of small user capacity of the load and high synchronization cost resulted from the clock synchronization method in existing technologies are solved, the insufficient user capacity of the load caused by the limit of the CPU architecture is avoided, and the bandwidth resource of the Ethernet is utilized to the maximum extent.

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