Abstract:
A detecting method of a detecting circuit with a plugged test lead. The method includes setting an operation mode of the detecting circuit by a recognizing unit, transmitting a signal to the recognizing unit by an oscillating unit when the test lead plugs or unplugs into a split contact jack, receiving the signal from the oscillating unit by the recognizing unit, and determining a condition of the detecting circuit, and sending a message to a user in accordance with the determining result of the recognizing unit. Further, the oscillating unit is stopped from oscillating and outputs a quiescent state voltage to the recognizing unit when the plugged test lead is inserted into the split contact jack.
Abstract:
A low error, plugged test lead detecting circuit for providing accurate current measurement and the method using the same. When a test lead of the plugged detecting circuit is plugged into a split contact jack of the plugged detecting circuit, the circuit stops oscillating during operations for a test lead detecting mode or a fuse open detecting mode. During the test lead detecting mode, if the test lead is plugged into the split contact jack, the oscillating unit stops automatically and outputs a quiescent state. Conversely, if the test lead is unplugged into the split contact jack, the oscillating unit generates a pre-determined frequency pulse according to the oscillating unit. During the fuse open detecting mode, the test lead is plugged into the split contact jack. If a fuse is presented, the oscillating unit stops automatically and outputs a quiescent state. If the fuse is not presented or blown, the oscillating unit generates a pre-determined frequency pulse according to the oscillating unit. During the current measurement mode, the protecting unit and the shunt form a series parallel circuit when the test lead is plugged into the split contact jack. The impedance of the shunt is negligible in comparison to the impedance of the protecting unit, and the voltage drop across the shunt is proportional to the injected current.
Abstract:
An electrochemical cell with a pressure relief vent formed in a metal plate disposed in at least one of the closed end and the open end of the container. The pressure relief vent has an annular ring that includes a reduced thickness groove, interrupted in at least two places by unthinned sections of the plate. When the vent opens to relieve pressure from within the cell, the area of the plate within the annular ring remains attached to the remainder of the plate by at least one of the unthinned sections. A can with such a pressure relief vent formed in the can bottom is useful as an electrochemical cell container.
Abstract:
An electrochemical battery cell with an electrical lead for electrical contact between one of the cell's electrodes and the side of the cell container. A portion of the lead, disposed between the electrode assembly and the side wall of the container, includes an initially non-planar shape that is in a partially deformed, compressed configuration within the cell to bias the lead against the internal surface of the side wall of the container, thereby applying sufficient force to provide good electrical contact between the electrode and the container. The initially non-planar shape can include one or more V-shaped or arc-shaped grooves, and the grooves can be disposed parallel to a longitudinal axis of the electrode assembly. Also disclosed is a process for making such a cell.
Abstract:
Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.