-
公开(公告)号：US20210019228A1
公开(公告)日：2021-01-21
申请号：US17060768
申请日：2020-10-01
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
-
公开(公告)号：US20200305031A1
公开(公告)日：2020-09-24
申请号：US16659714
申请日：2019-10-22
Inventor： Jae-Young LEE , Sung-Ik PARK , Heung-Mook KIM , Hyun-Jeong YIM
IPC: H04W36/00 , H04W36/14 , H04W36/30 , H04L12/26 , H04B17/336
Abstract: Disclosed herein are a broadcast signal reception method using network switching and an apparatus for the same. The broadcast signal reception method using network switching includes determining, by a broadcast signal reception apparatus, a network-switching time point based on a network-switching condition that is set in consideration of at least one of a characteristics of a broadcast signal received over a broadcast network during a preset time period and a continuity of packets received over the broadcast network during the preset time period, and receiving, by the broadcast signal reception apparatus, the broadcast signal by performing network switching to a broadband network at the network-switching time point.
-
93.发明申请公开(公告)号：US20200288469A1
公开(公告)日：2020-09-10
申请号：US16880545
申请日：2020-05-21
Inventor： Jae-Young LEE , Sung-Ik PARK , Sun-Hyoung KWON , Heung-Mook KIM , Nam-Ho HUR
IPC: H04W72/04 , H04L27/26 , H04J11/00 , H04L1/00 , H04L27/34 , H04W52/34 , H04L5/22 , H04L29/06 , H04W52/04
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
-
公开(公告)号：US20200235976A1
公开(公告)日：2020-07-23
申请号：US16652428
申请日：2018-05-24
Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , KOREA MARITIME UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
Inventor： Sung-Ik PARK , Jeong-Chang KIM , Jae-Young LEE , Sun-Hyoung KWON , Hyeong-Seok KIM , Heung-Mook KIM , Nam-Ho HUR
Abstract: Disclosed herein are an apparatus and method for decoding a bootstrap signal. The apparatus for decoding a bootstrap signal according to an embodiment of the present invention includes an operation unit for calculating the relative cyclic shift and the channel gain estimate of a received bootstrap signal and correcting the channel gain estimate using the relative cyclic shift, and a decoding unit for decoding the bootstrap signal using the corrected channel gain estimate.
-
公开(公告)号：US20200212938A1
公开(公告)日：2020-07-02
申请号：US16808288
申请日：2020-03-03
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
-
Patent Agency Ranking
96.发明申请公开(公告)号：US20200153519A1
公开(公告)日：2020-05-14
申请号：US16744421
申请日：2020-01-16
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC: H04H20/67 , H04L27/26 , H04L1/00 , H04L29/08 , H04H20/71 , H04W52/32 , H04H60/73 , H04J11/00 , H04H60/44 , H04H20/31
Abstract: An apparatus for transmitting broadcasting signal using transmitter identification scaled by 4-bit injection level code and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter, the transmitter identification signal scaled by an injection level code; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.
-
97.发明申请公开(公告)号：US20200052724A1
公开(公告)日：2020-02-13
申请号：US16658270
申请日：2019-10-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
Abstract: A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
-
公开(公告)号：US20190356340A1
公开(公告)日：2019-11-21
申请号：US16530758
申请日：2019-08-02
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
-
公开(公告)号：US20190356338A1
公开(公告)日：2019-11-21
申请号：US16527485
申请日：2019-07-31
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
-
公开(公告)号：US20190341940A1
公开(公告)日：2019-11-07
申请号：US16516514
申请日：2019-07-19
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
-
-
-
-
-
-
-
-
-
Search Results
228
records
(took 0.026 seconds)
