公开(公告)号：US07512919B2

公开(公告)日：2009-03-31

申请号：US11503200

申请日：2006-08-11

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing that is most useful in the inner loop of an automatic computer-aided design (CAD) synthesis or optimization tool. In the statistical re-timing, the delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated.

摘要翻译： 本发明是一种用于在电路中进行改变之后有效地并递增地更新数字电路的统计定时的系统和方法。 在电路中的一个或多个变化之后是有效回答的定时查询，构成在自动计算机辅助设计（CAD）综合或优化工具的内循环中最有用的定时模式。 在统计重新定时中，每个门或线的延迟被假设为由标称部分，由每个变化源参数化的相关随机部分和独立的随机部分组成。 考虑相关性。 包括早期模式和晚期模式时序; 处理组合和顺序电路; 静态CMOS以及动态逻辑系列。

公开(公告)号：US20060277513A1

公开(公告)日：2006-12-07

申请号：US11503200

申请日：2006-08-11

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing that is most useful in the inner loop of an automatic computer-aided design (CAD) synthesis or optimization tool. In the statistical re-timing, the delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated.

公开(公告)号：US07111260B2

公开(公告)日：2006-09-19

申请号：US10665092

申请日：2003-09-18

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing that is most useful in the inner loop of an automatic computer-aided design (CAD) synthesis or optimization tool. In the statistical re-timing, the delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated.

公开(公告)号：US07086023B2

公开(公告)日：2006-08-01

申请号：US10666470

申请日：2003-09-19

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for determining criticality probability of each node, edge and path of the timing graph of a digital circuit in the presence of delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The criticality determination complexity is linear in the size of the graph and the number of sources of variation. The invention includes a method for efficiently enumerating the critical path(s) that is/are most likely to be critical.

摘要翻译： 本发明是一种用于在存在延迟变化的情况下确定数字电路的时序图的每个节点，边缘和路径的临界概率的系统和方法。 假设每个门或线的延迟由标称部分，由每个变化源参数化的相关随机部分和独立的随机部分组成。 考虑相关性。 包括早期模式和晚期模式时序; 处理组合和顺序电路; 静态CMOS以及动态逻辑系列。 关键性决定复杂度在图形的大小和变异的来源数量上是线性的。 本发明包括一种用于有效地列举最可能是至关重要的关键路径的方法。

公开(公告)号：US07010763B2

公开(公告)日：2006-03-07

申请号：US10436213

申请日：2003-05-12

申请人： David J. Hathaway ,  Lawrence Kenneth Lange ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： David J. Hathaway ,  Lawrence Kenneth Lange ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.

摘要翻译： 公开了一种在数字集成电路或系统的设计中实现定时闭合的方法，通过选择要优化的电路或系统的部分以及在优化期间分析这种优化的影响的电路或系统的部分 处理。 优化部分将包括其设计参数将被改变的门，第一分析部分包括要重新计算其延迟和边缘电压的门，并且第二分析部分包括在优化期间重新计算其AT和RAT的门。 在这些部分之间的选定边界施加约束，以防止定时信息的不期望的传播，并确保优化期间使用的定时值的有效性。 通过这种选择，将降低对基础优化方法造成的问题的大小，从而允许更大的电路或系统被优化，并允许更快地执行优化。

公开(公告)号：US08122404B2

公开(公告)日：2012-02-21

申请号：US12388932

申请日：2009-02-19

申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

公开(公告)号：US07743355B2

公开(公告)日：2010-06-22

申请号：US11942034

申请日：2007-11-19

申请人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US20080307379A1

公开(公告)日：2008-12-11

申请号：US12196754

申请日：2008-08-22

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing that is most useful in the inner loop of an automatic computer-aided design (CAD) synthesis or optimization tool. In the statistical re-timing, the delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated.

摘要翻译： 本发明是一种用于在电路中进行改变之后有效地并递增地更新数字电路的统计定时的系统和方法。 在电路中的一个或多个变化之后是有效回答的定时查询，构成在自动计算机辅助设计（CAD）综合或优化工具的内循环中最有用的定时模式。 在统计重新定时中，每个门或线的延迟被假设为由标称部分，由每个变化源参数化的相关随机部分和独立的随机部分组成。 考虑相关性。 包括早期模式和晚期模式时序; 处理组合和顺序电路; 静态CMOS以及动态逻辑系列。

公开(公告)号：US20080172642A1

公开(公告)日：2008-07-17

申请号：US11622979

申请日：2007-01-12

申请人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

发明人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.

摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。

公开(公告)号：US20080140983A1

公开(公告)日：2008-06-12

申请号：US12020879

申请日：2008-01-28

申请人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

IPC分类号： G06F12/02

CPC分类号： G06F17/5031 ,  G06K9/6226 ,  G06K9/6247

摘要： A computer system for partitioning the columns of a matrix A. The computer system includes a processor and a memory unit coupled to the processor. Program code in the memory unit, when executed by the processor, implements the method. Matrix A is provided in a memory device and has n columns and m rows; wherein n is an integer of at least 3; and wherein m is an integer of at least 1. The n columns is partitioned into a closed group of p clusters, p being a positive integer of at least 2 and less than n. The partitioning includes an affinity-based merging of clusters of pairs of clusters of the matrix A based on an affinity between the clusters in each pair of clusters being merged. Each cluster consists of one or more columns of matrix A. The p clusters are stored in a computer-readable storage device.

摘要翻译： 一种用于分割矩阵A的列的计算机系统。计算机系统包括处理器和耦合到处理器的存储器单元。 当处理器执行时，存储器单元中的程序代码实现该方法。 矩阵A在存储器件中提供并具有n列和m行; 其中n为至少3的整数; 并且其中m是至少为1的整数。n列被划分成闭合的p个簇，p是至少为2且小于n的正整数。 基于被合并的每对簇中的簇之间的亲和度，分割包括矩阵A的聚类对的聚类的基于亲和度的合并。 每个簇由矩阵A的一个或多个列组成.P个簇存储在计算机可读存储设备中。