公开(公告)号：US07788617B2

公开(公告)日：2010-08-31

申请号：US12043455

申请日：2008-03-06

申请人： Adil Bhanji ,  Soroush Abbaspour ,  Peter Feldmann ,  Debjit Sinha

发明人： Adil Bhanji ,  Soroush Abbaspour ,  Peter Feldmann ,  Debjit Sinha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.

摘要翻译： 一种精确的方法来计算电容与电容相关的引脚上的电容。 该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。 产生来自压摆和输出负载的针电容表的RC / RLC网络。 所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。 方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。

公开(公告)号：US20100211922A1

公开(公告)日：2010-08-19

申请号：US12388932

申请日：2009-02-19

申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

公开(公告)号：US08122404B2

公开(公告)日：2012-02-21

申请号：US12388932

申请日：2009-02-19

申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

公开(公告)号：US08185371B2

公开(公告)日：2012-05-22

申请号：US12424400

申请日：2009-04-15

申请人： Adil Bhanji ,  Sean Michael Carey ,  Jack Dilullo ,  Prashant D Joshi ,  Don Richard Rozales ,  Vern Anthony Victoria ,  Albert Thomas Williams

发明人： Adil Bhanji ,  Sean Michael Carey ,  Jack Dilullo ,  Prashant D Joshi ,  Don Richard Rozales ,  Vern Anthony Victoria ,  Albert Thomas Williams

IPC分类号： G06F17/50 ,  G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  G06F1/00 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

摘要翻译： 建模系统包括具有在设计模型上执行静态时序分析（STA）的软件的处理器。 STA软件执行以缩短的时钟周期运行的静态时序分析（STA）来建模全周期时钟变化。 设计人员或其他实体通过对输出数据进行建模来解释缩短的STA运行数据的结果，以产生设计模型数据路径的松弛数据。 STA软件执行具有扩展时钟周期的STA运行，以便从全周期数据路径（FCDP）松弛数据自动分离半周期数据路径（HCDP）松弛数据。 全周期和半周期时钟可变性方法可以自动调整所有半周期数据路径（HCDP）的松弛数据，以考虑额外的半周期变化（AHCV）和半周期时钟边沿变化，这可能会对设计模型造成影响 硬件实现。

公开(公告)号：US08103997B2

公开(公告)日：2012-01-24

申请号：US12426492

申请日：2009-04-20

申请人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

发明人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.

摘要翻译： 用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。 在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。 采用互连模型订单减少来加速流程。 在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。

公开(公告)号：US20100269083A1

公开(公告)日：2010-10-21

申请号：US12426492

申请日：2009-04-20

申请人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

发明人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.

摘要翻译： 用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。 在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。 采用互连模型订单减少来加速流程。 在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。

公开(公告)号：US20100268522A1

公开(公告)日：2010-10-21

申请号：US12424400

申请日：2009-04-15

申请人： Adil Bhanji ,  Sean Michael Carey ,  Jack Dilullo ,  Prashant D Joshi ,  Don Richard Rozales ,  Vern Anthony Victoria ,  Albert Thomas Williams

发明人： Adil Bhanji ,  Sean Michael Carey ,  Jack Dilullo ,  Prashant D Joshi ,  Don Richard Rozales ,  Vern Anthony Victoria ,  Albert Thomas Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation. Designers use a sort of slack data for half cycle data paths (HCDP)s independent of the slack data for the full cycle data path (FCDP)s to modify or otherwise perform design changes to the design model prior to hardware implementation.

摘要翻译： 建模系统包括具有在设计模型上执行静态时序分析（STA）的软件的处理器。 STA软件执行以缩短的时钟周期运行的静态时序分析（STA）来建模全周期时钟变化。 设计人员或其他实体通过对输出数据进行建模来解释缩短的STA运行数据的结果，以产生设计模型数据路径的松弛数据。 STA软件执行具有扩展时钟周期的STA运行，以便从全周期数据路径（FCDP）松弛数据自动分离半周期数据路径（HCDP）松弛数据。 全周期和半周期时钟可变性方法可以自动调整所有半周期数据路径（HCDP）的松弛数据，以考虑额外的半周期变化（AHCV）和半周期时钟边沿变化，这可能会对设计模型造成影响 硬件实现。 设计师使用一种与半周期数据路径（HCDP）无关的松弛数据，独立于全周期数据路径（FCDP）的松弛数据，以在硬件实现之前修改或执行设计模型的设计更改。

公开(公告)号：US20090228850A1

公开(公告)日：2009-09-10

申请号：US12043455

申请日：2008-03-06

申请人： Adil Bhanji ,  Soroush Abbaspour ,  Peter Feldmann ,  Debjit Sinha

发明人： Adil Bhanji ,  Soroush Abbaspour ,  Peter Feldmann ,  Debjit Sinha

IPC分类号： G06F9/45

CPC分类号： G06F17/5031

摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.

摘要翻译： 一种精确的方法来计算电容与电容相关的引脚上的电容。 该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。 产生来自压摆和输出负载的针电容表的RC / RLC网络。 所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。 方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。