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    Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits
    1.
    发明申请
    Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits 有权
    执行VLSI电路分层时序分析的统计时序抽象方法

    公开(公告)号：US20100211922A1

    公开(公告)日：2010-08-19

    申请号：US12388932

    申请日：2009-02-19

    申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

    摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

    Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits
    2.
    发明授权
    Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits 有权
    对VLSI电路的分层定时分析执行统计时序抽象

    公开(公告)号：US08122404B2

    公开(公告)日：2012-02-21

    申请号：US12388932

    申请日：2009-02-19

    申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

    摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

    Method and apparatus for efficient incremental statistical timing analysis and optimization
    4.
    发明授权
    Method and apparatus for efficient incremental statistical timing analysis and optimization 有权
    用于高效增量统计时序分析和优化的方法和装置

    公开(公告)号：US08104005B2

    公开(公告)日：2012-01-24

    申请号：US12244512

    申请日：2008-10-02

    申请人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.

    摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。

    Performing statistical timing analysis with non-separable statistical and deterministic variations
    7.
    发明授权
    Performing statistical timing analysis with non-separable statistical and deterministic variations 失效
    用不可分的统计和确定性变化进行统计时序分析

    公开(公告)号：US08418107B2

    公开(公告)日：2013-04-09

    申请号：US12943541

    申请日：2010-11-10

    申请人： Jeffrey G Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Jeffrey G Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/504 ,  G06F2217/10 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.

    摘要翻译： 在一个实施例中，本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。 用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆，其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数，以及第二工艺参数 其与第一过程参数是统计的且不可分离的，并且使用定时数量执行单个定时运行，其中单个定时运行产生到达时间，所需的到达时间和定时偏移在输出，锁存器和电路节点 集成电路芯片。 计算的到达时间，所需的到达时间和时间休息可以被计算为确定性变化的角落值，以便获得相应角落处的延迟和炖菜的统计模型。

    METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION
    10.
    发明申请
    METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION 有权
    有效增量统计时序分析与优化的方法与装置

    公开(公告)号：US20100088658A1

    公开(公告)日：2010-04-08

    申请号：US12244512

    申请日：2008-10-02

    申请人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.

    摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。