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91.发明申请Systems and Methods for Error Correction Using Low Density Parity Check Codes Using Multiple Layer Check Equations 有权使用多层校验方程的低密度奇偶校验码的纠错系统和方法公开(公告)号：US20120331369A1
公开(公告)日：2012-12-27
申请号：US13167775
申请日：2011-06-24
申请人： Zongwang Li
发明人： Zongwang Li
CPC分类号： H03M13/1142 , H03M13/033 , H03M13/036 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.
摘要翻译： 本发明的各种实施例提供了用于生成代码格式的系统和方法。 所讨论的一种方法包括：接收具有大于1的行宽度和列高度的第一矩阵; 将循环体结合到第一基质的第一柱中; 测试用于捕集组的第一列，其中识别至少一个捕集组; 选择一个值以减轻所识别的捕获集合; 以及用第二矩阵增加第一矩阵以产生复合矩阵。 第二矩阵在第一列中具有所选择的值，并且其中所识别的捕获集合被减轻。
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公开(公告)号：US08775896B2
公开(公告)日：2014-07-08
申请号：US13369468
申请日：2012-02-09
申请人： Zongwang Li , Chung-Li Wang , Changyou Xu
发明人： Zongwang Li , Chung-Li Wang , Changyou Xu
IPC分类号： H03M13/00
CPC分类号： H03M13/658 , H03M13/1122 , H03M13/1131 , H03M13/1171 , H03M13/2957 , H03M13/6325 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.
摘要翻译： 本发明的各种实施例提供用于解码非二进制LDPC码的系统和方法。 例如，公开了一种低密度奇偶校验数据解码器，其包括可变节点处理器，其可操作以至少部分地基于校验节点到可变节点消息向量来执行变量节点更新;校验节点处理器，可操作以执行校验节点更新，以及 生成检查节点到可变节点消息向量，以及调度器，用于当对于给定的解码迭代执行变量节点更新时，使得变量节点处理器使用来自多个解码迭代的可变节点消息向量的校验节点。
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公开(公告)号：US20130212447A1
公开(公告)日：2013-08-15
申请号：US13369468
申请日：2012-02-09
申请人： Zongwang Li , Chung-Li Wang , Changyou Xu
发明人： Zongwang Li , Chung-Li Wang , Changyou Xu
CPC分类号： H03M13/658 , H03M13/1122 , H03M13/1131 , H03M13/1171 , H03M13/2957 , H03M13/6325 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.
摘要翻译： 本发明的各种实施例提供用于解码非二进制LDPC码的系统和方法。 例如，公开了一种低密度奇偶校验数据解码器，其包括可变节点处理器，其可操作以至少部分地基于校验节点到可变节点消息向量来执行变量节点更新;校验节点处理器，可操作以执行校验节点更新，以及 生成检查节点到可变节点消息向量，以及调度器，用于当对于给定的解码迭代执行变量节点更新时，使得变量节点处理器使用来自多个解码迭代的可变节点消息向量的校验节点。
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公开(公告)号：US08711620B2
公开(公告)日：2014-04-29
申请号：US13588043
申请日：2012-08-17
CPC分类号： G11C7/02 , G11C7/1006 , G11C16/26 , G11C2029/5002
摘要： An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.
摘要翻译： 描述了被配置为修改信号以至少从信号中去除噪声部分的装置。 在一个或多个实现中，该设备是协作过滤模块，其被配置为通信地耦合到具有多个存储器单元块的存储器阵列。 存储器阵列被配置为提供表示存储在多个存储单元块内的数据的信号。 协作过滤模块被配置为当发出多个存储单元块的读取操作时，确定与多个存储器单元块相关联的噪声分布，并产生基于噪声分布的噪声预测。 协同过滤模块还被配置为使用噪声预测来修改信号以至少基本上从信号中去除噪声。
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公开(公告)号：US20140050023A1
公开(公告)日：2014-02-20
申请号：US13588043
申请日：2012-08-17
CPC分类号： G11C7/02 , G11C7/1006 , G11C16/26 , G11C2029/5002
摘要： An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.
摘要翻译： 描述了被配置为修改信号以至少从信号中去除噪声部分的装置。 在一个或多个实现中，该设备是协作过滤模块，其被配置为通信地耦合到具有多个存储器单元块的存储器阵列。 存储器阵列被配置为提供表示存储在多个存储单元块内的数据的信号。 协作过滤模块被配置为当发出多个存储单元块的读取操作时，确定与多个存储器单元块相关联的噪声分布，并产生基于噪声分布的噪声预测。 协同过滤模块还被配置为使用噪声预测来修改信号以至少基本上从信号中去除噪声。
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96.发明授权Systems and methods for error correction using low density parity check codes using multiple layer check equations 有权使用多层校验方程的低密度奇偶校验码进行纠错的系统和方法公开(公告)号：US08566665B2
公开(公告)日：2013-10-22
申请号：US13167775
申请日：2011-06-24
申请人： Zongwang Li
发明人： Zongwang Li
CPC分类号： H03M13/1142 , H03M13/033 , H03M13/036 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.
摘要翻译： 本发明的各种实施例提供了用于生成代码格式的系统和方法。 所讨论的一种方法包括：接收具有大于1的行宽度和列高度的第一矩阵; 将循环体结合到第一基质的第一柱中; 测试用于捕集组的第一列，其中识别至少一个捕集组; 选择一个值以减轻所识别的捕获集合; 以及用第二矩阵增加第一矩阵以产生复合矩阵。 第二矩阵在第一列中具有所选择的值，并且其中所识别的捕获集合被减轻。
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公开(公告)号：US20140052893A1
公开(公告)日：2014-02-20
申请号：US13585933
申请日：2012-08-15
申请人： Fan Zhang , Zongwang Li , Ming Jin , Erich F. Haratsch
发明人： Fan Zhang , Zongwang Li , Ming Jin , Erich F. Haratsch
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file. The controller stores the data at a data storage segment having a physical address and associates the physical address with the logical address and a file identifier for the file. The controller receives a second write request including data and the logical address associated with the file. The controller stores the data at a second data storage segment having a second physical address and associates the second physical address with the logical address and the file identifier. When a file delete request for the file is received, the controller identifies the first physical address and the second physical address using the file identifier and erases the information stored at the first data storage segment and the second data storage segment based upon the file identification.
摘要翻译： 设备包括非易失性存储器和控制器。 控制器接收包括数据和与文件相关联的逻辑地址的写入请求。 控制器将数据存储在具有物理地址的数据存储段处，并将物理地址与逻辑地址和文件的文件标识符相关联。 控制器接收包括数据和与文件相关联的逻辑地址的第二写入请求。 控制器将数据存储在具有第二物理地址的第二数据存储段，并将第二物理地址与逻辑地址和文件标识符相关联。 当接收到文件的文件删除请求时，控制器使用文件标识符识别第一物理地址和第二物理地址，并且基于文件标识擦除存储在第一数据存储段和第二数据存储段的信息。
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公开(公告)号：US20130120169A1
公开(公告)日：2013-05-16
申请号：US13295160
申请日：2011-11-14
申请人： Zongwang Li , Lei Chen , Chung-Li Wang
发明人： Zongwang Li , Lei Chen , Chung-Li Wang
CPC分类号： H03M13/1122 , H03M13/112 , H03M13/116 , H03M13/658
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data encoder circuit. The data encoder circuit is operable to apply an encoding algorithm to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set. The last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix.
摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，公开了包括数据编码器电路的数据处理系统。 数据编码器电路可操作以根据包括第一行和最后一行的多层代码结构将编码算法应用于输入数据集，以产生编码数据集。 在编码数据集中表示的多层代码结构的最后一行符合一个单位矩阵。
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公开(公告)号：US20130046958A1
公开(公告)日：2013-02-21
申请号：US13213751
申请日：2011-08-19
申请人： Fan Zhang , Zongwang Li , Wu Chang
发明人： Fan Zhang , Zongwang Li , Wu Chang
CPC分类号： G06F9/30 , H03M13/1111 , H03M13/1128 , H03M13/1515 , H03M13/2957 , H03M13/41 , H03M13/6331 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data decoder circuit and a local iteration adjustment circuit. The data decoder circuit is operable to perform a number of local iterations on a decoder input to yield a data output. The local iteration adjustment circuit is operable to generate a limit on the number of local iterations performed by the data decoder circuit
摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了一种数据处理电路，其包括：数据解码器电路和局部迭代调整电路。 数据解码器电路可操作以在解码器输入上执行多次局部迭代以产生数据输出。 本地迭代调整电路可操作以产生由数据解码器电路执行的局部迭代次数的限制
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