公开(公告)号：US08108876B2

公开(公告)日：2012-01-31

申请号：US11846101

申请日：2007-08-28

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

IPC分类号： G06F9/46 ,  G06F15/173

CPC分类号： G06F9/505 ,  G06F9/5038 ,  G06F9/52 ,  G06F9/522 ,  G06F9/546 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2209/508 ,  G06F2209/509

摘要： Mechanisms for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing work loads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI Load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

摘要翻译： 提供了修改执行消息传递接口（MPI）任务的一个或多个处理器的操作的机制。 提供了调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待周期。 每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

公开(公告)号：US20090198956A1

公开(公告)日：2009-08-06

申请号：US12024662

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  Edward J. Seminaro ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  Edward J. Seminaro ,  William E. Speight

IPC分类号： G06F15/80 ,  G06F15/76 ,  G06F9/00

CPC分类号： H04L45/12 ,  H04L45/06 ,  H04L49/109 ,  H04L49/25

摘要： A system and method are provided for implementing a two-tier full-graph interconnect architecture. In order to implement a two-tier full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the two-tier full-graph interconnect architecture. Data is then transmitted from one processor to another within the two-tier full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor chip identifier associated with a target processor to which the data is to be transmitted.

摘要翻译： 提供了一种用于实现两层全图互连架构的系统和方法。 为了实现两层全图互连架构，多个处理器彼此耦合以创建多个超节点。 然后，多个超节点被耦合在一起以创建双层全图互连体系结构。 基于指定至少一个超级节点的寻址方案和与要发送数据的目标处理器相关联的处理器芯片标识符，在两层全图互连架构内将数据从一个处理器发送到另一个处理器。

公开(公告)号：US20090064167A1

公开(公告)日：2009-03-05

申请号：US11846154

申请日：2007-08-28

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

IPC分类号： G06F9/46

CPC分类号： G06F9/522 ,  G06F9/5083

摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.

摘要翻译： 提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。 提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

公开(公告)号：US20090063815A1

公开(公告)日：2009-03-05

申请号：US11845223

申请日：2007-08-27

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F15/17381

摘要： A method, computer program product, and system are provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.

摘要翻译： 提供了一种执行集体操作的方法，计算机程序产品和系统。 在第一处理器书中的母处理器的硬件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包括母处理器 和其他处理器。 在母处理器的硬件中，多个处理器在逻辑上被布置为分层结构中的多个节点。 基于层次结构将集体操作发送到多个处理器。 在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。