公开(公告)号：US20250077087A1

公开(公告)日：2025-03-06

申请号：US18954404

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F13/42

Abstract: A storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. The storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. A data generator is connected to the network interface. A local host system is connected to the host interface to control access, made via the network interface. The data generator can send bulk data to the network interface. The computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. A central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.

公开(公告)号：US12238015B2

公开(公告)日：2025-02-25

申请号：US17866318

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: H04L49/00 ,  H04L49/103 ,  H04L49/90 ,  H04L67/1097

Abstract: A memory sub-system connectable to a microprocessor to provide network storage services. The memory sub-system has a random-access memory configured with: first queues for the microprocessor and a network interface; second queues for the microprocessor and a processing device; and third queues for the processing device and a storage device. The processing device is configured to: generate first control messages and first data messages from packets received by the network interface; place the first control messages into the first queues for the microprocessor; and place the first data messages into the third queues for the storage device. The microprocessor processes the first control messages to implement security and administrative functions and place second control messages in the second queues. The storage device is configured to retrieve the first data messages from the third queues and second control messages from the second queues for processing.

公开(公告)号：US20250021253A1

公开(公告)日：2025-01-16

申请号：US18770896

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Sampath Ratnam

IPC: G06F3/06

Abstract: Various embodiments provide for processing write requests on a memory system based on queue identifiers associated with the write requests. In particular, input data streams can be received and stored by submission queues of a memory system, and write requests in the input data streams can be separated and processed based on queue identifiers associated with the submission queues using an inline approach for writing data on the memory system, an offline approach for writing data on the memory system, or both.

公开(公告)号：US12197754B2

公开(公告)日：2025-01-14

申请号：US18337873

申请日：2023-06-20

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A host system to query, during booting up of the host system, a superblock size in a connected memory sub-system. The host system can place write requests into separate streams and send the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively. The host system can allocate, a plurality of log buffers for the streams respectively and record, into the log buffers, sequences of logical addresses as in the streams respectively. The host system can trim a stream, among the plurality of streams, by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a log buffer for the stream, causing the memory sub-system to free at least one superblock.

公开(公告)号：US12153798B2

公开(公告)日：2024-11-26

申请号：US17866348

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F13/42

Abstract: A storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. The storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. A data generator is connected to the network interface. A local host system is connected to the host interface to control access, made via the network interface. The data generator can send bulk data to the network interface. The computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. A central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.

公开(公告)号：US20240378111A1

公开(公告)日：2024-11-14

申请号：US18641290

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan R. Hinkle ,  Luca Bert

IPC: G06F11/10

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

公开(公告)号：US20240377964A1

公开(公告)日：2024-11-14

申请号：US18641296

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan R. Hinkle ,  Luca Bert

IPC: G06F3/06

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems that support and provide redundant coverage for multiple hosts are described. The grouped set of chained subsystems can provide dedicated storage locations for each of the multiple hosts during normal operations. When one of the hosts fail, the grouped set can reconfigure the internal accessing scheme, thereby allowing the surviving host to see and access locations and data that was initially assigned to the failed host.

公开(公告)号：US12131041B2

公开(公告)日：2024-10-29

申请号：US17680183

申请日：2022-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0683

Abstract: A system includes one or more memory devices and a processing device coupled to the memory device(s) to perform operations including receiving a first set of data items from a host system to be programmed to the one or more memory devices. The operations include determining, in view of a first zone group identifier associated with the first set of data items, that each data item of the first set of data items is to be programed to one or more zones associated with a first zone group identified by the first zone group identifier. The operations include identifying a first set of zones across the one or more memory devices that match a size associated with the first zone group and that satisfy a programming parallelism criterion. The operations include programming each of the first set of data items to memory cells residing at the identified first set of zones.

公开(公告)号：US12111761B2

公开(公告)日：2024-10-08

申请号：US17688506

申请日：2022-03-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F12/0808 ,  G06F12/0871

CPC classification number: G06F12/0808 ,  G06F12/0871 ,  G06F2212/50

Abstract: A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.

公开(公告)号：US12086468B2

公开(公告)日：2024-09-10

申请号：US18200851

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph H. Steinmetz

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A host command is received designating a first interface standard at a first port for exposing a storage element implemented by a non-volatile memory device and a second interface standard at a second port for exposing a persistent memory region (PMR) implemented as a power protected region of a volatile memory device. The non-volatile memory device and the volatile memory device are associated with a first switch for implementing the first interface standard and a second switch for implementing the second interface standard. The first interface standard supports one or more alternate protocols implemented by the second interface standard. The storage element is exposed by designating the first interface standard at the first port and the PMR by designating the second interface standard at the second port. A segment of the PMR is allocated as a cacheable memory marked as visible through, and shared through, the second interface standard.