公开(公告)号：US11264337B2

公开(公告)日：2022-03-01

申请号：US16702104

申请日：2019-12-03

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/367 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die and a frame. The semiconductor die is disposed over the substrate. The frame is disposed over the substrate, wherein the frame is adjacent to the semiconductor die, and the upper surface of the frame is lower than the upper surface of the semiconductor die.

公开(公告)号：US20210273317A1

公开(公告)日：2021-09-02

申请号：US17321914

申请日：2021-05-17

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/38 ,  H01Q9/16

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

公开(公告)号：US11043730B2

公开(公告)日：2021-06-22

申请号：US16387354

申请日：2019-04-17

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/38 ,  H01Q9/16

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

公开(公告)号：US11024954B2

公开(公告)日：2021-06-01

申请号：US16399659

申请日：2019-04-30

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01Q1/38 ,  H01Q9/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/66

Abstract: A method of forming a semiconductor package structure includes providing a first wafer-level package structure having a die region surrounded by a scribe line region. The first wafer-level package structure includes a first encapsulating layer, a first redistribution layer (RDL) structure formed on the first encapsulating layer, a first antenna element formed in the first RDL structure and corresponding to the die region, and a semiconductor die in the first encapsulating layer and corresponding to the die region. A second wafer-level package structure is bonded onto the first RDL structure using a first adhesive layer. The second wafer-level package structure includes a second encapsulating layer attached to the first adhesive layer, and a second antenna element formed on the second encapsulating layer. The second antenna element and the first antenna element form a pitch antenna after the bonding of the second wafer-level package structure.

公开(公告)号：US20200303352A1

公开(公告)日：2020-09-24

申请号：US16899335

申请日：2020-06-11

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Yu-Hua Huang ,  Wei-Che Huang ,  Ming-Tzong Yang

IPC: H01L25/065 ,  H01L23/00

Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.

公开(公告)号：US20200294948A1

公开(公告)日：2020-09-17

申请号：US16888845

申请日：2020-05-31

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

IPC: H01L23/00 ,  H01L23/498

Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.

公开(公告)号：US10573615B2

公开(公告)日：2020-02-25

申请号：US14173976

申请日：2014-02-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US20200006289A1

公开(公告)日：2020-01-02

申请号：US16563919

申请日：2019-09-08

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.

公开(公告)号：US10424563B2

公开(公告)日：2019-09-24

申请号：US15066241

申请日：2016-03-10

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.

公开(公告)号：US10361173B2

公开(公告)日：2019-07-23

申请号：US15365217

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ming-Tzong Yang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L25/18 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package has a semiconductor die having pads thereon, first vias disposed on the first semiconductor die, the first vias coupled to the pads. A second semiconductor package is stacked on the first semiconductor package and includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface, a first memory die mounted on the bump-attach surface, coupled to the body, and a second memory die mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first memory die is different from the number of input/output (I/O) pins of the second memory die.