公开(公告)号：US11876959B2

公开(公告)日：2024-01-16

申请号：US17956093

申请日：2022-09-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Che Wei Kuo ,  Hai Wei Sun ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/14 ,  H04N19/159 ,  H04N19/105 ,  H04N19/176

CPC classification number: H04N19/105 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.

公开(公告)号：US11812024B2

公开(公告)日：2023-11-07

申请号：US17396984

申请日：2021-08-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/13 ,  H04N19/136 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

CPC classification number: H04N19/13 ,  H04N19/136 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

Abstract: An encoder includes circuitry and memory connected thereto. The circuitry, in operation: encodes an image; when encoding the image: binarizes coefficient information of the image; controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and outputs a bitstream including the binary data string to which arithmetic encoding has been applied or has not been applied; and when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is to be applied to the binary data string and a determined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is to be applied to the binary data string and the determined condition is satisfied; and binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is to be applied to the binary data string.

公开(公告)号：US11716470B2

公开(公告)日：2023-08-01

申请号：US17583768

申请日：2022-01-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/169 ,  H04N19/82

CPC classification number: H04N19/117 ,  H04N19/132 ,  H04N19/188 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes information for deriving a parameter into a header of a bitstream; filters reconstructed samples in a first image using a filtering process, to generate a second image; determines whether the parameter has a predefined value; encodes a third image using the second image when the parameter has the predefined value; and encodes the third image using the first image when the parameter does not have the predefined value.

公开(公告)号：US11700375B2

公开(公告)日：2023-07-11

申请号：US17564510

申请日：2021-12-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/13 ,  H04L65/70 ,  H04L65/75 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

CPC classification number: H04N19/13 ,  H04L65/70 ,  H04L65/75 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.

公开(公告)号：US11665370B2

公开(公告)日：2023-05-30

申请号：US17379302

申请日：2021-07-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/169 ,  H04N19/423 ,  H04N19/46

CPC classification number: H04N19/70 ,  H04N19/188 ,  H04N19/423 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: writes, into a sequence parameter set which is header information of a sequence, video usability information syntax which is information for realizing an additional function in display of an image, and syntax different from the video usability information syntax. The syntax includes at least one parameter related to display timing of the image.

公开(公告)号：US11528508B2

公开(公告)日：2022-12-13

申请号：US17589393

申请日：2022-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chu Tong Wang ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167 ,  H04N19/17 ,  H04N19/186

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US11503318B2

公开(公告)日：2022-11-15

申请号：US17388694

申请日：2021-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei Kuo ,  Chong Soon Lim ,  Han Boon Teo ,  Jing Ya Li ,  Hai Wei Sun ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/00 ,  H04N19/44 ,  H04N19/105 ,  H04N19/117 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/46

Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.

公开(公告)号：US11425385B2

公开(公告)日：2022-08-23

申请号：US17173024

申请日：2021-02-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/169

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

公开(公告)号：US11095883B2

公开(公告)日：2021-08-17

申请号：US17173634

申请日：2021-02-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.