Modulation coding
    91.
    发明授权
    Modulation coding 有权
    调制编码

    公开(公告)号:US07719444B2

    公开(公告)日:2010-05-18

    申请号:US12265829

    申请日:2008-11-06

    申请人: Roy D. Cideciyan

    发明人: Roy D. Cideciyan

    IPC分类号: H03M7/00

    摘要: Methods and apparatus are provided for modulation coding of input data. In a first scheme, a modulation encoder applies a modulation code to input data to produce an (L,K)-constrained encoded bit-sequence, where K is maximum run-length of 0's, and L is the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence. Then, a precoder effects 1/(1⊕D4) preceding of the encoded bit-sequence. In a second scheme, a modulation encoder applies a modulation code to the input data to produce a K-constrained encoded bit-sequence. In this scheme, a precoder then effects 1/(1⊕D⊕D2⊕D3) preceding of the encoded bit-sequence. In both schemes, the effect of the precoder is to produce a precoded sequence in which, in addition to other constraints, the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value CVFO.

    摘要翻译: 提供了用于输入数据的调制编码的方法和装置。 在第一方案中,调制编码器将调制码应用于输入数据以产生(L,K)约束编码比特序列,其中K是最大游程长度0,L是最大游程长度0 在编码比特序列的奇数和偶数交织中。 然后,预编码器在编码的比特序列之前实现1 /(1⊕D4)。 在第二方案中,调制编码器将调制码施加到输入数据以产生K受限的编码比特序列。 在该方案中,预编码器然后实现编码比特序列之前的1 /(1⊕D⊕D2⊕D3)。 在这两种方案中,预编码器的作用是产生一个预编码序列,其中除了其他限制之外,可变频率振荡器模式的最大长度被限制在预定值CVFO。

    Packet data transmission in code-division multiple access communication systems
    93.
    发明授权
    Packet data transmission in code-division multiple access communication systems 失效
    码分多址通信系统中的分组数据传输

    公开(公告)号:US06181683B2

    公开(公告)日:2001-01-30

    申请号:US08973264

    申请日:1997-12-03

    IPC分类号: H04B7216

    摘要: A system and method for the wireless transmission of data packets in a code division multiple access communication system wherein one of the code division multiple access channels (PRCH) is used in a time-shared fashion for the transmission of the data packets from several transmitting stations (MSy, MSz) to a receiving station (BS). A request is sent from a transmitting station (MSy) to the corresponding receiving station (BS) of the communication system indicating the destination address to which data packet(s) are to be routed. Then, registering the transmitting station (MSy) and assigning an unique virtual connection identifier (VCIy) to it. Next, the transmitting station (MSy) is attached to the code division multiple access channel (PRCH) used for the transmission of data packets. Then, listening to the downlink of the code division multiple access channel (PRCH) used for the transmission of data packets until the corresponding receiving station (BS) broadcasts that it will be “idle” such that a random access to the code division multiple access channel (PRCH) used for the transmission of data packets is allowed in the next frame. Next, the transnmission power of the transmitting station (MSy) is ramped up during the next frame until a certain power level is reached. The data packet(s) and the virtual connection identifier (VCIy) are transmitted over the uplink of the code division multiple access channel (PRCH) used for the transmission of data packets to the receiving station (BS). The data packet(s) are routed to the destination address. Access to the code division multiple access channel (PRCH) used for the transmission of data packets is controller by a multiple access protocol based on carrier sensing and collision detection (CSMA/CD).

    摘要翻译: 一种用于在码分多址通信系统中无线传输数据分组的系统和方法,其中码分多址信道(PRCH)中的一个以时分方式用于从多个发射台发送数据分组 (MSy,MSz)到接收站(BS)。请求从发送站(MSy)发送到通信系统的相应接收站(BS),指示数据分组将要的目的地地址 然后,注册发送站(MSy)并向其分配唯一的虚拟连接标识符(VCIy)。接下来,发送站(MSy)附加到用于数据传输的码分多址信道(PRCH) 然后,监听用于数据分组传输的码分多址信道(PRCH)的下行链路,直到相应的接收站(BS)广播它将为“空闲” 使得在下一帧中允许对用于传输数据分组的码分多址信道(PRCH)的随机访问。接下来,发送站(MSy)的传输功率在下一帧期间增加,直到 数据包和虚拟连接标识符(VCIy)通过用于向接收站(BS)发送数据包的码分多址信道(PRCH)的上行链路发送。 数据包被路由到目的地址。用于传输数据包的码分多址信道(PRCH)的访问是基于载波侦听和冲突检测(CSMA / CD)的多址协议的控制器, 。

    Flexible encoding method and architecture for high speed data
transmission and storage
    94.
    发明授权
    Flexible encoding method and architecture for high speed data transmission and storage 失效
    用于高速数据传输和存储的灵活编码方法和架构

    公开(公告)号:US5245339A

    公开(公告)日:1993-09-14

    申请号:US838614

    申请日:1992-02-19

    申请人: Roy D. Cideciyan

    发明人: Roy D. Cideciyan

    IPC分类号: G11B20/14 H03M5/14 H04L25/49

    摘要: In data transmission and storage using encoding through finite-state machines, the feedback link that updates each finite-state machine after each encoding step presents a bottleneck for a high speed implementation. The invention solves this problem for a class of finite-state machines that includes the encoder for the known 8B/10B Widmer-Franaszek code. The architecture consists of parallel finite-state units that are pipelined to run at a relatively low clock frequency. State updating is broken down into a feedforward part and a feedback part. In the feedback part, the state of each unit can be updated with a single operation. This allows efficient implementation of the finite-state encoder for practically any data rate just by appropriate pipelining and parallel processing.

    RLL encoder and decoder with pipelined plural byte processing
    95.
    发明授权
    RLL encoder and decoder with pipelined plural byte processing 失效
    RLL编码器和解码器与管道字节处理

    公开(公告)号:US5177482A

    公开(公告)日:1993-01-05

    申请号:US729264

    申请日:1991-07-12

    摘要: For encoding a stream of k-bit data bytes into a stream of m-bit code bytes satisfying given constraints, a coding principle and coder apparatus are disclosed which allow pipelined and parallel handling of the byte stream. Each data byte DB and an associated coder state indicator S are together converted into a code byte CB. The coder state indicator S(i) to be associated with a data byte DB(i) is obtained by logically combining the coder state indicator S(i-1) of the preceding data byte DB(i-1) and a state transition indicator T(i-1) derived from the latter. This allows the simultaneous generation of all coder state indicators S for a whole group (a word) of data bytes, thereby enabling the parallel and pipelined operation of the coder.