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公开(公告)号：US10775489B2
公开(公告)日：2020-09-15
申请号：US15665663
申请日：2017-08-01
IPC分类号： G01S13/28 , G06F17/14 , G01S7/41 , G01S13/536 , G01S13/931 , G01S13/34 , G01S7/35 , G06F17/13 , H04N5/232
摘要： A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.
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公开(公告)号：US20200225318A1
公开(公告)日：2020-07-16
申请号：US16836836
申请日：2020-03-31
IPC分类号： G01S7/40 , G01S13/931 , G01S7/35
摘要： A radar system is provided that includes a receive channel including a complex baseband and a processor coupled to the receive channel to receive a first plurality of digital intermediate frequency (IF) samples from an in-band (I) channel of the complex baseband and a corresponding second plurality of digital IF samples from a quadrature (Q) channel of the complex baseband, wherein the processor is configured to execute instructions to compute at least one failure metric based on the first plurality of digital IF samples and the second plurality of digital IF samples.
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公开(公告)号：US10659078B2
公开(公告)日：2020-05-19
申请号：US16200061
申请日：2018-11-26
摘要： A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.
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公开(公告)号：US10649069B2
公开(公告)日：2020-05-12
申请号：US15635659
申请日：2017-06-28
摘要： The disclosure provides a radar apparatus for estimating a position and a velocity of the plurality of obstacles. The radar apparatus includes a local oscillator that generates a first signal. A first transmit unit receives the first signal from the local oscillator and generates a first transmit signal. A frequency shifter receives the first signal from the local oscillator and generates a second signal. A second transmit unit receives the second signal and generates a second transmit signal. The frequency shifter provides a frequency offset to the first signal based on a routing delay mismatch to generate the second signal such that the first transmit signal is phase coherent with the second transmit signal.
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公开(公告)号：US10598767B2
公开(公告)日：2020-03-24
申请号：US16253790
申请日：2019-01-22
发明人： Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
摘要： Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
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公开(公告)号：US20200041551A1
公开(公告)日：2020-02-06
申请号：US16597612
申请日：2019-10-09
发明人： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
摘要： A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.
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公开(公告)号：US20200025871A1
公开(公告)日：2020-01-23
申请号：US16114490
申请日：2018-08-28
发明人： Karthik Subburaj , Karthik Ramasubramanian , Sriram Murali , Sreekiran Samala , Krishnanshu Dandu
摘要： A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.
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公开(公告)号：US10234542B2
公开(公告)日：2019-03-19
申请号：US14870129
申请日：2015-09-30
发明人： Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
摘要： Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
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公开(公告)号：US20190004167A1
公开(公告)日：2019-01-03
申请号：US16121689
申请日：2018-09-05
发明人： Sandeep Rao , Karthik Subburaj , Brian Ginsburg , Karthik Ramasubramanian , Jawaharlal Tangudu , Sachin Bharadwaj
摘要： The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.
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公开(公告)号：US20180172813A1
公开(公告)日：2018-06-21
申请号：US15665663
申请日：2017-08-01
CPC分类号： G01S13/282 , G01S7/354 , G01S7/415 , G01S13/343 , G01S13/536 , G01S13/931 , G01S2007/356 , G06F17/13 , G06F17/142 , H04N5/23296
摘要： A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.
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