公开(公告)号：US20190318964A1

公开(公告)日：2019-10-17

申请号：US16297702

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Han-Tsun Wang ,  Chang-Hung Chen ,  Po-Yu Yang ,  Mei-Ying Fan ,  Mu-Kai Tsai ,  Guan-Shyan Lin ,  Tsz-Hui Kuo ,  Cheng-Hsiung Chen

IPC: H01L21/8234 ,  H01L27/11 ,  H01L27/088

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

公开(公告)号：US12255245B2

公开(公告)日：2025-03-18

申请号：US18590985

申请日：2024-02-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions. A top surface of the first vertical portion in and a top surface of one of the first horizontal portions are coplanar.

公开(公告)号：US20250040195A1

公开(公告)日：2025-01-30

申请号：US18917979

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer and including a device region, and a charge trap layer in the substrate and extending between the insulating layer and the substrate and directly under the device region. The charge trap layer includes a plurality of n-type first doped regions and a plurality of p-type second doped regions alternately arranged and directly in contact with each other to form a plurality of interrupted depletion junctions.

公开(公告)号：US12142676B2

公开(公告)日：2024-11-12

申请号：US18227329

申请日：2023-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a high electron mobility transistor includes the steps of forming an epitaxial stack on a substrate, forming a gate structure on the epitaxial stack, forming an insulating layer covering the epitaxial stack and the gate structure, forming a passivation layer on the insulating layer, forming an opening on the gate structure and through the passivation layer to expose the insulating layer, and removing a portion of the insulating layer through the opening to form an air gap between the gate structure and the passivation layer.

公开(公告)号：US20240355920A1

公开(公告)日：2024-10-24

申请号：US18761282

申请日：2024-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0649 ,  H01L29/66462 ,  H01L29/6656

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and the gate structure, and an air gap between the passivation layer and the gate structure. The gate structure includes a semiconductor gate layer and a metal gate layer on the semiconductor gate layer. The air gap is in direct contact with a sidewall of the passivation layer, a sidewall of the metal gate layer, a sidewall and a top surface of the semiconductor gate layer.

公开(公告)号：US12051740B2

公开(公告)日：2024-07-30

申请号：US17367640

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0649 ,  H01L29/66462 ,  H01L29/6656

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.

公开(公告)号：US20240136417A1

公开(公告)日：2024-04-25

申请号：US18395616

申请日：2023-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.

公开(公告)号：US11961889B2

公开(公告)日：2024-04-16

申请号：US17951058

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/41 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

公开(公告)号：US20240072153A1

公开(公告)日：2024-02-29

申请号：US18506101

申请日：2023-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L29/7786

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

公开(公告)号：US20230317840A1

公开(公告)日：2023-10-05

申请号：US18206620

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/47 ,  H01L21/285 ,  H01L29/205 ,  H01L29/423

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/475 ,  H01L21/28581 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/42372 ,  H01L29/4238

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate.