公开(公告)号：US20190318964A1

公开(公告)日：2019-10-17

申请号：US16297702

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Han-Tsun Wang ,  Chang-Hung Chen ,  Po-Yu Yang ,  Mei-Ying Fan ,  Mu-Kai Tsai ,  Guan-Shyan Lin ,  Tsz-Hui Kuo ,  Cheng-Hsiung Chen

IPC: H01L21/8234 ,  H01L27/11 ,  H01L27/088

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

公开(公告)号：US10276446B1

公开(公告)日：2019-04-30

申请号：US15976848

申请日：2018-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Han-Tsun Wang ,  Chang-Hung Chen ,  Po-Yu Yang ,  Mei-Ying Fan ,  Mu-Kai Tsai ,  Guan-Shyan Lin ,  Tsz-Hui Kuo ,  Cheng-Hsiung Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

公开(公告)号：US09761302B1

公开(公告)日：2017-09-12

申请号：US15092613

申请日：2016-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chang-Hung Chen ,  Chun-Hsien Huang ,  Han-Tsun Wang ,  Jheng-Tai Yan ,  Yu-Tse Kuo

IPC: G11C11/34 ,  G11C11/417 ,  G11C11/412 ,  H01L27/105

CPC classification number: G11C11/417 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1104

Abstract: A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.