公开(公告)号：US06196734B1

公开(公告)日：2001-03-06

申请号：US09410955

申请日：1999-10-05

申请人： Michael K. Templeton ,  Bharath Rangarajan

发明人： Michael K. Templeton ,  Bharath Rangarajan

IPC分类号： G03D500

CPC分类号： G03D13/006

摘要： A system for regulating temperature of a developer is provided. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the developer. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the developer. The measuring system provides developer temperature related data to a processor which determines the temperature of the respective portions of the developer. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the developer.

摘要翻译： 提供了一种用于调节显影剂温度的系统。 该系统包括多个光纤，每个光纤将辐射引导到显影剂的相应部分。 从相应部分反射的辐射由处理收集的辐射的测量系统收集。 反射的辐射表示显影剂各部分的温度。 测量系统将显影剂温度相关数据提供给确定显影剂各部分的温度的处理器。 该系统还包括多个加热装置; 每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置，以便调节显影剂各部分的温度。

公开(公告)号：US06187666B1

公开(公告)日：2001-02-13

申请号：US09328148

申请日：1999-06-08

申请人： Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan ,  Christopher F. Lyons ,  Sanjay K. Yedur ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan ,  Christopher F. Lyons ,  Sanjay K. Yedur ,  Ramkumar Subramanian

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/76831 ,  H01L2221/1063

摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.

摘要翻译： 本发明涉及在绝缘材料层中制造互连线和通孔的方法。 在绝缘材料层中形成通孔。 形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。 执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。 通孔和沟槽填充有导电金属。

公开(公告)号：US6030868A

公开(公告)日：2000-02-29

申请号：US33916

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan ,  Mark T. Ramsbey

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan ,  Mark T. Ramsbey

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.

摘要翻译： 一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。 在多晶硅层上形成多层介电层。 蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。 多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。 形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。