公开(公告)号：US5448496A

公开(公告)日：1995-09-05

申请号：US270234

申请日：1994-07-01

Applicant: Michael R. Butts ,  Jon A. Batcheller

Inventor： Michael R. Butts ,  Jon A. Batcheller

IPC: G06F17/50 ,  H03K17/693 ,  H03K17/735

CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F17/5068

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract translation: 多个电子可重构门阵列（ERCGA）逻辑芯片经由可重配置互连互连，并且大数字网络的电子表示被转换为在互连芯片上采取暂时的实际操作硬件形式。 可重构互连允许在互连芯片上实现的数字网络随意改变，使系统非常适合于各种目的，包括仿真，原型设计，执行和计算。 可重配置互连可以包括由专用于互连功能的ERCGA芯片形成的部分交叉开关，其中每个这样的互连ERCGA连接到多个逻辑芯片的至少一个但不是全部的引脚。 其他可重配置互连拓扑也是详细的。

公开(公告)号：US5425036A

公开(公告)日：1995-06-13

申请号：US947308

申请日：1992-09-18

Applicant: Dick L. Liu ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Kenneth S. K. Choi

Inventor： Dick L. Liu ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Kenneth S. K. Choi

IPC: G06F17/50 ,  G06F15/60

CPC classification number: G06F17/5027

Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

Abstract translation: 改进的电子设计自动化（EDA）系统采用现场可编程门阵列（FPGA）来仿真原型电路设计。 电路网表文件被下载到FPGA，以配置FPGA模拟原型电路的功能表示。 为了检查电路网表是否正确地实现，通过向其施加输入向量并且将所得到的FPGA的输出与从先前的仿真提供的输出向量进行比较来功能地测试FPGA。 如果FPGA不通过这样的矢量比较，则通过在输入向量中插入“回读”触发指令来调试FPGA，优选地对应于所应用的矢量流中的故障点。 使用这种读回信号修改输入向量会导致在重复功能测试时捕获每个FPGA中的锁存器和触发器的内部状态。 这种内部状态信息对调试FPGA非常有用，特别方便，因为不需要重新编译电路网表。 采用FPGA使用回读特性的类似方法可用于调试耦合到目标系统的FPGA，仿真运行期间似乎失败。