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    Timing of a circuit design
    2.
    发明授权
    Timing of a circuit design 有权
    电路设计的时序

    公开(公告)号：US07917881B1

    公开(公告)日：2011-03-29

    申请号：US11725188

    申请日：2007-03-15

    Applicant: Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

    Inventor： Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/84

    Abstract: Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

    Abstract translation: 公开了改进电路设计的时序和/或产量。 时序和产量改进通常是电路设计中的竞争目标，因为时序改进通常是由减少电容耦合而产生的，而产量改进通常会增加电容耦合。 因此，时序和产量改进之间的权衡是电路设计和/或优化过程的一部分。

    Optimizing a circuit design
    3.
    发明授权
    Optimizing a circuit design 有权
    优化电路设计

    公开(公告)号：US07739630B1

    公开(公告)日：2010-06-15

    申请号：US11725191

    申请日：2007-03-15

    Applicant: Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

    Inventor： Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/84

    Abstract: Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

    Abstract translation: 公开了改进电路设计的时序和/或产量。 时序和产量改进通常是电路设计中的竞争目标，因为时序改进通常是由减少电容耦合而产生的，而产量改进通常会增加电容耦合。 因此，时序和产量改进之间的权衡是电路设计和/或优化过程的一部分。

    Method and apparatus for debugging reconfigurable emulation systems
    4.
    发明授权
    Method and apparatus for debugging reconfigurable emulation systems 失效
    用于调试可重构仿真系统的方法和装置

    公开(公告)号：US5425036A

    公开(公告)日：1995-06-13

    申请号：US947308

    申请日：1992-09-18

    Applicant: Dick L. Liu ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Kenneth S. K. Choi

    Inventor： Dick L. Liu ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Kenneth S. K. Choi

    IPC: G06F17/50 ,  G06F15/60

    CPC classification number: G06F17/5027

    Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

    Abstract translation: 改进的电子设计自动化（EDA）系统采用现场可编程门阵列（FPGA）来仿真原型电路设计。 电路网表文件被下载到FPGA，以配置FPGA模拟原型电路的功能表示。 为了检查电路网表是否正确地实现，通过向其施加输入向量并且将所得到的FPGA的输出与从先前的仿真提供的输出向量进行比较来功能地测试FPGA。 如果FPGA不通过这样的矢量比较，则通过在输入向量中插入“回读”触发指令来调试FPGA，优选地对应于所应用的矢量流中的故障点。 使用这种读回信号修改输入向量会导致在重复功能测试时捕获每个FPGA中的锁存器和触发器的内部状态。 这种内部状态信息对调试FPGA非常有用，特别方便，因为不需要重新编译电路网表。 采用FPGA使用回读特性的类似方法可用于调试耦合到目标系统的FPGA，仿真运行期间似乎失败。

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