公开(公告)号：US5425036A

公开(公告)日：1995-06-13

申请号：US947308

申请日：1992-09-18

Applicant: Dick L. Liu ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Kenneth S. K. Choi

Inventor： Dick L. Liu ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Kenneth S. K. Choi

IPC: G06F17/50 ,  G06F15/60

CPC classification number: G06F17/5027

Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

Abstract translation: 改进的电子设计自动化（EDA）系统采用现场可编程门阵列（FPGA）来仿真原型电路设计。 电路网表文件被下载到FPGA，以配置FPGA模拟原型电路的功能表示。 为了检查电路网表是否正确地实现，通过向其施加输入向量并且将所得到的FPGA的输出与从先前的仿真提供的输出向量进行比较来功能地测试FPGA。 如果FPGA不通过这样的矢量比较，则通过在输入向量中插入“回读”触发指令来调试FPGA，优选地对应于所应用的矢量流中的故障点。 使用这种读回信号修改输入向量会导致在重复功能测试时捕获每个FPGA中的锁存器和触发器的内部状态。 这种内部状态信息对调试FPGA非常有用，特别方便，因为不需要重新编译电路网表。 采用FPGA使用回读特性的类似方法可用于调试耦合到目标系统的FPGA，仿真运行期间似乎失败。

公开(公告)号：US5049814A

公开(公告)日：1991-09-17

申请号：US457910

申请日：1989-12-27

Applicant: Robert M. Walker, III ,  Dick L. Liu

Inventor： Robert M. Walker, III ,  Dick L. Liu

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/3193

CPC classification number: G01R31/31937

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

公开(公告)号：US5177440A

公开(公告)日：1993-01-05

申请号：US714962

申请日：1991-07-11

Applicant: Robert M. Walker, III ,  Dick L. Liu

Inventor： Robert M. Walker, III ,  Dick L. Liu

IPC: G01R31/3193

CPC classification number: G01R31/31937

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Abstract translation: 提供了一种以高工作速度测试集成电路的方法，其适用于诸如ASIC之类的顺序逻辑电路。 通用ASIC测试仪将测试矢量应用于被测集成电路。 逻辑输入信号保持不变，并且一系列高速时钟信号（时钟脉冲串）被施加到集成电路的时钟端子。 这些时钟信号以希望测试集成电路的速度提供。 然后，在时钟脉冲串之后，观察输出端子以确定器件是否处于预期状态（通过仿真确定）。 重复该过程，直到没有其他输出端改变状态，然后可以重新初始化该设备并启动另一系列状态改变。 因此，电路中的每个路径都可以通过传统的低速测试仪以高速度进行测试。