公开(公告)号：US20060221952A1

公开(公告)日：2006-10-05

申请号：US11096365

申请日：2005-04-01

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli

IPC: H04J3/24 ,  H04L12/56 ,  H04L12/28

CPC classification number: H04L1/0052 ,  H04L1/0061

Abstract: A system and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) that is coupled to a host. The method includes receiving a part of a frame, wherein a plurality of parts of a frame constitute a entire frame. Next, parse the part of a frame before receiving the entire frame. The HEA computes a checksum of the part of a frame. The HEA filters the part of a frame based on a logical, port-specific policy and transmits the checksum to the host.

Abstract translation: 用于在耦合到主机的主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法。 该方法包括接收帧的一部分，其中帧的多个部分构成整个帧。 接下来，在接收整个帧之前解析帧的一部分。 HEA计算帧的一部分的校验和。 HEA基于逻辑，端口特定策略过滤帧的一部分，并将校验和传送到主机。

公开(公告)号：US20060206939A1

公开(公告)日：2006-09-14

申请号：US11422087

申请日：2006-06-05

Applicant: Chih-Jen Chang ,  Shi-Ming Zhao ,  Shih-Wei Chien

Inventor： Chih-Jen Chang ,  Shi-Ming Zhao ,  Shih-Wei Chien

IPC: G06F12/14 ,  G06F11/00 ,  G06F12/16 ,  G06F15/18 ,  G08B23/00

CPC classification number: G06F21/563 ,  G06F21/564 ,  H04L51/12 ,  H04L63/1416 ,  H04L63/145

Abstract: Methods and systems for processing multiple levels of data in system security approaches are disclosed. In one embodiment, a first set and a second set of resources are selected to iteratively and independently reverse multiple levels of format conversions on the payload portions of a data unit from a first file and a data unit from a second file, respectively. The first file and the second file are associated with a first transport connection and a second transport connection, respectively. Upon completion of the aforementioned reversal operations, the payload portions of a first reversed data unit and a second reversed data unit, which correspond to the data unit of the first file and the data unit of the second file, respectively, are inspected for suspicious patterns prior to any aggregation of the data units of the first file or the second file.

Abstract translation: 公开了在系统安全方法中处理多级数据的方法和系统。 在一个实施例中，选择第一组和第二组资源以分别从第一文件和来自第二文件的数据单元反复地和独立地反转数据单元的有效载荷部分上的多个格式转换级别。 第一文件和第二文件分别与第一传输连接和第二传输连接相关联。 在完成上述反转操作时，分别对应于第一文件的数据单元和第二文件的数据单元的第一反向数据单元和第二反向数据单元的有效载荷部分被检查为可疑图案 在第一文件或第二文件的数据单元的任何聚合之前。

公开(公告)号：US20060206684A1

公开(公告)日：2006-09-14

申请号：US11076218

申请日：2005-03-09

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

IPC: G06F12/00 ,  G06F9/34

CPC classification number: H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

公开(公告)号：US20060200615A1

公开(公告)日：2006-09-07

申请号：US11070758

申请日：2005-03-02

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Harm Hofstee ,  Jens Leenstra ,  Hans-Werner Tast ,  Fabrice Verplanken ,  Colin Verrilli

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Harm Hofstee ,  Jens Leenstra ,  Hans-Werner Tast ,  Fabrice Verplanken ,  Colin Verrilli

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0864

Abstract: Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.

Abstract translation: 公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。 更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。 基于观察结果，可以确定最小化碰撞的最佳映射。

公开(公告)号：US20060039376A1

公开(公告)日：2006-02-23

申请号：US10868725

申请日：2004-06-15

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

Abstract: A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

Abstract translation: 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。