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    Systems and methods for weighted best effort scheduling
    8.
    发明申请
    Systems and methods for weighted best effort scheduling 失效
    加权最佳努力调度的系统和方法

    公开(公告)号：US20060233177A1

    公开(公告)日：2006-10-19

    申请号：US11108485

    申请日：2005-04-18

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    IPC分类号： H04L12/56 ,  H04L12/54

    CPC分类号： H04L47/568 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L47/527

    摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.

    摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，三入口日历结构提供加权最佳努力调度。 多个不同的流中的每一个具有相关的进度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

    Flexible control block format for frame description and management
    9.
    发明申请
    Flexible control block format for frame description and management 失效
    灵活的控制块格式，用于帧描述和管理

    公开(公告)号：US20060215677A1

    公开(公告)日：2006-09-28

    申请号：US11091245

    申请日：2005-03-28

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： H04L12/26 ,  H04L12/56

    CPC分类号： H04L12/5601 ,  H04L49/90 ,  H04L2012/5642 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5681

    摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.

    摘要翻译： 用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。 每个单独的数据包由FCB描述和控制。 与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。 当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。 当帧在输入队列中时，格式不需要第三个字。

    Systems and methods for multi-frame control blocks
    10.
    发明申请
    Systems and methods for multi-frame control blocks 有权

    公开(公告)号：US20060206684A1

    公开(公告)日：2006-09-14

    申请号：US11076218

    申请日：2005-03-09

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    IPC分类号： G06F12/00 ,  G06F9/34

    CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

    摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.