公开(公告)号：US20080006854A1

公开(公告)日：2008-01-10

申请号：US11425542

申请日：2006-06-21

申请人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7848 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.

摘要翻译： 本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。 这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。 优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面 。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。 具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

公开(公告)号：US20070275510A1

公开(公告)日：2007-11-29

申请号：US11420318

申请日：2006-05-25

申请人： Huajie Chen ,  Judson R. Holt ,  Rangarajan Jagannathan ,  Wesley C. Natzle ,  Michael R. Sievers ,  Richard S. Wise

发明人： Huajie Chen ,  Judson R. Holt ,  Rangarajan Jagannathan ,  Wesley C. Natzle ,  Michael R. Sievers ,  Richard S. Wise

IPC分类号： H01L21/8232 ,  H01L21/8234 ,  H01L21/335

CPC分类号： H01L29/66636 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

摘要翻译： 公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。 蚀刻半导体层以形成切割栅极介电层的凹部。 低能量植入物形成晕轮。 然后，执行COR预清洁，并且通过外延沉积填充凹部。 外延可以被原位掺杂或随后植入以形成源/漏扩展。 或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。 在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。 或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。