Method and system for compressing data which allows access to data without full uncompression
    101.
    发明授权
    Method and system for compressing data which allows access to data without full uncompression 失效
    用于压缩数据的方法和系统,允许在没有完全解压缩的情况下访问数据

    公开(公告)号:US06438556B1

    公开(公告)日:2002-08-20

    申请号:US09210503

    申请日:1998-12-11

    IPC分类号: G06F1730

    摘要: A system and method for compressing data on a computer system is disclosed. The method and system include separating the data into a plurality of segments. The plurality of segments includes a plurality of unique segments. The method and system also include providing a plurality of code words. Each of the plurality of code words corresponds to a unique segment of the plurality of unique segments. The method and system also include providing a representation of the data. The representation includes the plurality of code words for the plurality of segments. The plurality of code words in the representation replaces the plurality of segments. As a result, the data in the representation could be accessed randomly.

    摘要翻译: 公开了一种用于在计算机系统上压缩数据的系统和方法。 该方法和系统包括将数据分成多个段。 多个段包括多个唯一段。 该方法和系统还包括提供多个码字。 多个代码字中的每一个对应于多个唯一段的唯一段。 该方法和系统还包括提供数据的表示。 该表示包括多个段的多个码字。 该表示中的多个代码字代替多个段。 因此,表示中的数据可以随机访问。

    Apparatus and method for compressing pseudo-random data using distribution approximations
    102.
    发明授权
    Apparatus and method for compressing pseudo-random data using distribution approximations 失效
    使用分布近似来压缩伪随机数据的装置和方法

    公开(公告)号:US06411228B1

    公开(公告)日:2002-06-25

    申请号:US09666331

    申请日:2000-09-21

    申请人: Nadeem Malik

    发明人: Nadeem Malik

    IPC分类号: H03M734

    CPC分类号: H03M7/30

    摘要: An apparatus and method for compressing pseudo-random data is provided. The apparatus and method make use of stochastic distribution models to generate approximations of the input data. A data sequence obtained from the stochastic distribution models is compared to the input data sequence to generate a difference data sequence. The difference data sequence tends to be less “random” than the input data sequence and is thus, a candidate for compression using pattern repetition. The difference data sequence is compressed using standard compression techniques and stored as a compressed data file along with information identifying the stochastic distribution model used and any parameters of the stochastic distribution model, including seed value and the like. When decompressing a data file compressed in the manner described above, the compressed difference data sequence is decompressed and a data sequence is generated using the identified stochastic distribution model and model parameters. The data sequence generated is then added to the difference data sequence to generate the original input data sequence.

    摘要翻译: 提供了一种用于压缩伪随机数据的装置和方法。 该装置和方法利用随机分布模型来产生输入数据的近似值。 将从随机分布模型获得的数据序列与输入数据序列进行比较以产生差分数据序列。 差异数据序列倾向于比输入数据序列“随机”,因此是使用模式重复的压缩候选。 使用标准压缩技术压缩差异数据序列,并将其作为压缩数据文件以及识别所使用的随机分布模型的信息和随机分布模型的任何参数(包括种子值等)存储。 当解压缩以上述方式压缩的数据文件时,压缩差分数据序列被解压缩并且使用所识别的随机分布模型和模型参数生成数据序列。 然后将生成的数据序列添加到差数据序列以生成原始输入数据序列。

    Method and apparatus for creating and manipulating a compressed binary decision diagram in a data processing system
    103.
    发明授权
    Method and apparatus for creating and manipulating a compressed binary decision diagram in a data processing system 失效
    用于在数据处理系统中创建和操纵压缩二进制决策图的方法和装置

    公开(公告)号:US06385617B1

    公开(公告)日:2002-05-07

    申请号:US09413903

    申请日:1999-10-07

    申请人: Nadeem Malik

    发明人: Nadeem Malik

    IPC分类号: G06F1730

    CPC分类号: G06F17/504 Y10S707/99942

    摘要: A method and apparatus in a data processing system for manipulating a set of binary decision diagrams. A plurality of segments is created from the set of binary decision diagrams. A group of compression codes is associated with the set of segments, wherein the group of compression codes form a compressed data structure representing the set of binary decision diagrams.

    摘要翻译: 一种用于操纵一组二进制决策图的数据处理系统中的方法和装置。 从该组二进制决策图中创建多个段。 一组压缩码与一组段相关联,其中该组压缩码形成表示二进制判定图的集合的压缩数据结构。

    Method and system for detecting the issuance and completion of processor
instructions
    104.
    发明授权
    Method and system for detecting the issuance and completion of processor instructions 失效
    用于检测处理器指令的发布和完成的方法和系统

    公开(公告)号:US5802573A

    公开(公告)日:1998-09-01

    申请号:US606904

    申请日:1996-02-26

    IPC分类号: G06F11/26 G06F17/50 G06F13/00

    CPC分类号: G06F17/5022 G06F11/261

    摘要: A method and apparatus for verifying memory coherency of a simulated computer system. A verification logic unit is used for detecting the issuance of load and store instructions from the simulated system. Targets (registers or memory locations) representing the detected instructions are then stored in queues, and marked (colored) as not having been executed. After a detected instruction has been executed and completed, the corresponding target in the queue is marked as being completed. During every clock cycle of the apparatus, the verification logic unit monitors the queues for entries (Targets) marked as completed, which are then discarded.

    摘要翻译: 一种用于验证模拟计算机系统的存储器一致性的方法和装置。 验证逻辑单元用于检测来自仿真系统的负载和存储指令的发布。 表示检测到的指令的目标(寄存器或存储器位置)然后被存储在队列中,并被标记(彩色)为未被执行。 检测到的指令执行完成后,队列中的相应目标被标记为完成。 在装置的每个时钟周期期间,验证逻辑单元监视队列中的标记为已完成的条目(Targets),然后将其丢弃。

    Flexible pipeline for interlock removal
    105.
    发明授权
    Flexible pipeline for interlock removal 失效
    柔性管道用于互锁拆除

    公开(公告)号:US5778208A

    公开(公告)日:1998-07-07

    申请号:US575738

    申请日:1995-12-18

    IPC分类号: G06F9/38 G06F13/42

    CPC分类号: G06F9/3824

    摘要: A flexible pipeline for reducing performance limiting pipeline interlocks in the execution of programs. The pipeline architecture includes for each pipeline a fetch stage, a decode stage, an execution stage, a hybrid memory/execution stage, and a write back stage. When the result from the execution stage of a first pipeline is not available to a second pipeline until the write back stage of the first pipeline as a consequence of an interlock, the execution stage of the second pipeline may be delayed at least one execution cycle so that the executable functions are performed in the hybrid memory/execution stage or fourth stage of the second pipeline. The result from the execution stage is obtained either by a calculation of the effective address of a memory location or by performing arithmetic/logical unit (ALU) functions. The third stage of operation of the second pipeline carries out a null operation when the execute operation is performed in the fourth stage as a consequence of, for example, a load instruction being followed by a use instruction thereby resulting in a pipeline interlock.

    摘要翻译: 一种灵活的管道,用于在执行程序时降低性能限制管道互锁。 流水线架构包括对于每个流水线的取指阶段,解码阶段,执行阶段,混合存储器/执行阶段和回写阶段。 当第一流水线的执行阶段的结果不可用于第二流水线直到作为联锁的结果的第一流水线的回写阶段时,第二流水线的执行阶段可以被延迟至少一个执行周期 可执行功能在第二管道的混合存储器/执行级或第四级中执行。 通过计算存储器位置的有效地址或通过执行算术/逻辑单元(ALU)功能来获得执行阶段的结果。 第二管线的第三阶段在第四阶段执行执行操作时执行空操作,这是由于例如在加载指令之后是使用指令而导致管道互锁的结果。