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1.发明授权Method and system for reduction of XOR/XNOR subexpressions in structural design representations 有权在结构设计表示中减少XOR / XNOR子表达式的方法和系统公开(公告)号：US07831937B2
公开(公告)日：2010-11-09
申请号：US11955112
申请日：2007-12-12
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。 从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减 设计包含减少数量的异或门。 确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为 减少设计。
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2.发明授权Computer program product for verification of digital designs using case-splitting via constrained internal signals 有权用于通过限制内部信号通过案例分解验证数字设计的计算机程序产品公开(公告)号：US07458048B2
公开(公告)日：2008-11-25
申请号：US11945069
申请日：2007-11-26
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译： 公开了一种验证数字设计的方法。 该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。 然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。 该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序验证第二数字设计。
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公开(公告)号：US07421669B2
公开(公告)日：2008-09-02
申请号：US11236451
申请日：2005-09-27
CPC分类号： G06F17/504
摘要： A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译： 一种用于生成用于验证集成电路设计的约束的方法包括识别设计的网表（N）中的目标并创建网表的过近似抽象（N'）。 通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。 然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。 对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。 创建过近似抽象可能包括用随机门替换顺序门。 识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。
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4.发明授权Method and system for reduction of and/or subexpressions in structural design representations 失效在结构设计表示中减少和/或次表达的方法和系统公开(公告)号：US07380221B2
公开(公告)日：2008-05-27
申请号：US11086721
申请日：2005-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于减少包含AND和OR门的结构设计表示中的子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含与门的电子电路。 选择用于从一组适用的简化模式进行初始设计的第一简化模式，其中所述简化模式是AND / OR简化模式，并且执行根据第一简化模式的初始设计的简化以生成缩减设计 。 确定减小设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为简化的设计 。
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5.发明授权Method for heuristic preservation of critical inputs during sequential reparameterization 失效在连续重新参数化过程中启发式保存关键输入的方法公开(公告)号：US07370298B2
公开(公告)日：2008-05-06
申请号：US11105617
申请日：2005-04-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system, and computer program product for preserving critical inputs. According to an embodiment of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements are received. A cut of said initial design including one or more cut gates is identified, and a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements is computed. Said relation is synthesized to form a gate set, and an abstracted design is formed from said gate set. Verification is performed on said abstracted design to generate verification results.
摘要翻译： 一种用于保存关键输入的方法，系统和计算机程序产品。 根据本发明的实施例，接收包括一个或多个不能被消除的主要输入，可被消除的一个或多个主要输入，一个或多个目标以及一个或多个状态元素的初始设计。 识别包括一个或多个切割门的所述初始设计的切割，以及根据所述一个或多个主要输入而不能被消除的一个或多个可生产到所述一个或多个切割门的值的关系，所述一个或多个主要 可以消除的输入和所述一个或多个状态元素被计算。 所述关系被合成以形成栅极集合，并且从所述栅极集合形成抽象设计。 对所述抽象设计进行验证以产生验证结果。
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公开(公告)号：US07322017B2
公开(公告)日：2008-01-22
申请号：US11011245
申请日：2004-12-14
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译： 公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。 该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。
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7.发明授权Method and system for formal unidirectional bus verification using synthesizing constrained drivers 有权使用合成约束驱动程序进行正式单向总线验证的方法和系统公开(公告)号：US07305636B2
公开(公告)日：2007-12-04
申请号：US11065601
申请日：2005-02-24
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G06F17/5022 , G06F17/504
摘要： A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.
摘要翻译： 公开了一种用于执行验证的方法，系统和计算机程序产品。 创建对设计的高级描述，并从设计的高级描述合成约束的驱动程序。 测试台是从设计的高级描述和受限制的驱动程序生成的，并且在测试台上进行正式的等效性来执行验证。
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公开(公告)号：US07010485B1
公开(公告)日：2006-03-07
申请号：US09498234
申请日：2000-02-03
CPC分类号： G10L15/04 , G10L2015/088
摘要： A system, method, and computer program product for locating an audio segment includes an input device for transmitting an input sample indicative of the audio segment and a media player for playing audio information stored on the storage device. The system further includes a sample converter to generate a digitized representation of the input sample and a digitized representation of the audio information on the storage device. The digitized representation of the input sample may include a diphthong sequence indicative of the diphthong components of the input sample. In this embodiment, an audio converter of the system generates an audio content diphthong sequence. The system may further include a comparator configured to detect a match between the input sample diphthong sequence and a portion of the audio content diphthong sequence.
摘要翻译： 用于定位音频段的系统，方法和计算机程序产品包括用于发送指示音频段的输入样本的输入设备和用于播放存储在存储设备上的音频信息的媒体播放器。 该系统还包括采样转换器，用于生成输入样本的数字化表示和存储设备上的音频信息的数字化表示。 输入样本的数字化表示可以包括指示输入样本的双向分量的二次序列。 在本实施例中，系统的音频转换器产生音频内容双向序列。 系统还可以包括比较器，其被配置为检测输入样本二重序列与音频内容二重序列的一部分之间的匹配。
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公开(公告)号：US06980957B1
公开(公告)日：2005-12-27
申请号：US09460830
申请日：1999-12-14
CPC分类号： G10L19/0018
摘要： An audio transmission system and an associated method are disclosed, the system includes a transmitting device suitable for converting an audio signal to a digitized signal, a receiving device suitable for receiving transmissions from the transmitting device, and a phonetic analyzer suitable for comparing the digitized signal to a set of digitized signals stored in a first dictionary. The phonetic analyzer is adapted to transmit, in lieu of the digitized signal, an index value associated with the digitized signal to a receiving device in response to detecting a match between the digitized signal and one of the first dictionary entries. The phonetic analyzer is further adapted to assign an index value to the digitized signal and to store the digitized signal and its corresponding digitized signal in an entry of the first dictionary in response to detecting no match between the digitized signal and any of the first dictionary entries. The phonetic analyzer may be configured to compress the index value prior to transmission. The receiving device includes a second dictionary and a dictionary controller for receiving the index value and the corresponding digitized signal and for storing the index value and the corresponding index value in the second dictionary. Upon detecting an index value that matches to an index value in the second dictionary, the receiving device may be configured to retrieve the corresponding digitized signal from the second dictionary. The phonetic analyzer may assign index values that are indicative of the corresponding digitized signals such that index values assigned to similar digitized signals are similar and index values assigned to dissimilar digitized signals are dissimilar. In this embodiment, upon detecting an index value that fails to match to an index value in the secondary dictionary, the dictionary controller determines a closest matching index value and retrieves the digitized signal corresponding to closest matching index value from the second dictionary.
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公开(公告)号：US06816826B1
公开(公告)日：2004-11-09
申请号：US09679780
申请日：2000-10-05
申请人： Flemming Andersen , Jason Raymond Baumgartner , Kenneth Douglas Klapproth , Steven Leonard Roberts
发明人： Flemming Andersen , Jason Raymond Baumgartner , Kenneth Douglas Klapproth , Steven Leonard Roberts
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A logic network is simulated, including partitioning logic operations into domains and ranking the operations. Some operations are dependent on source operations from other domains. Pairs of operations having common dependencies are then separated by at least as many operations as the total number of operations in the domains of the respective source operations. All operations are then merged into an order having a certain relation to the respective domain orderings, but omitting nop's inserted to achieve desired separation. Then pairs of operations having common dependency are again separated, this time making advantageous use of overlaps, so that nop's are reduced, to improve simulation time. Due to separations, after one value is computed for one instance of an operation depending on a source operation, a next value is computed for the source operation before computing the next instance of an operation depending on the source operation.
摘要翻译： 模拟逻辑网络，包括将逻辑运算划分为域并对其进行排序。 一些操作依赖于其他域的源操作。 至少具有共同依赖关系的一组操作通过至少与各个源操作的域中的操作总数相同的操作分开。 然后将所有操作合并成与各个域排序具有一定关系的顺序，但省略插入的nop以实现期望的分离。 然后，具有共同依赖性的操作对再次被分离，这次有利地使用重叠，使得nop被减少，以提高模拟时间。 由于分离，在根据源操作对一个操作实例计算一个值之后，根据源操作计算下一个操作实例之前，为源操作计算下一个值。
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