公开(公告)号：US20230083877A1

公开(公告)日：2023-03-16

申请号：US17477250

申请日：2021-09-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/32

Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

公开(公告)号：US11513994B2

公开(公告)日：2022-11-29

申请号：US17148953

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/362 ,  G06F13/40

Abstract: Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

公开(公告)号：US20220255313A1

公开(公告)日：2022-08-11

申请号：US17172870

申请日：2021-02-10

Applicant: QUALCOMM INCORPORATED

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Georgios Konstantinos Paparrizos ,  Joshua Warner

IPC: H02H9/00 ,  H01R13/66 ,  H02H1/00 ,  H02M3/08

Abstract: Power delivery may be controlled to help prevent arcing when a data cable supplying power from a power source device to a power sink device is disconnected. The presence of a user in proximity to a connection between a cable plug and a cable receptacle may be detected. The level of a power signal being conveyed from the power source to the power sink may be reduced in response to the detection.

公开(公告)号：US20220179814A1

公开(公告)日：2022-06-09

申请号：US17116454

申请日：2020-12-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Yiftach Benjamini

IPC: G06F13/38 ,  G06F13/42

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

公开(公告)号：US11334134B2

公开(公告)日：2022-05-17

申请号：US17037984

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Naveen Kumar Narala ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun

IPC: G06F1/28 ,  G06F13/36

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

公开(公告)号：US11119790B2

公开(公告)日：2021-09-14

申请号：US16507947

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Lalan Jee Mishra

IPC: G06F9/445 ,  G06F1/10 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

公开(公告)号：US11119696B2

公开(公告)日：2021-09-14

申请号：US16508136

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F3/06 ,  G06F9/30 ,  G06F13/42

Abstract: Systems, methods, and apparatus for increasing register space on a slave device are described. A method performed at a device coupled to a serial bus includes receiving a datagram from a serial bus, the datagram including a command directed to a first register address in a first page of registers, writing data in a payload of the datagram to a second register address in a second page of registers when the command is a write command, and reading data from the second register address in the second page of registers when the command is a read command. The second register address is identified in the datagram when the command is a write command.

公开(公告)号：US20210181788A1

公开(公告)日：2021-06-17

申请号：US16717838

申请日：2019-12-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F1/14 ,  G06F1/3234 ,  H04L12/40

Abstract: Single-counter, multi-trigger systems and methods in communication systems consolidate tracking of multiple trigger events into a single counter in place of plural counters. The single counter may track multiple trigger events for a single triggered element. Likewise, the single counter may track trigger events for a plurality of triggered elements. By consolidating tracking of trigger events with reference to a single counter, the size of the circuit may be reduced and power savings may be achieved.

公开(公告)号：US10592441B2

公开(公告)日：2020-03-17

申请号：US15960356

申请日：2018-04-23

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Christopher Kong Yee Chun ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

公开(公告)号：US10545886B2

公开(公告)日：2020-01-28

申请号：US16167193

申请日：2018-10-22

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/376

Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.