公开(公告)号：US07529655B2

公开(公告)日：2009-05-05

申请号：US12106416

申请日：2008-04-21

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

摘要翻译： 根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。 在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。 然后接收并处理从模拟设计获得的仿真结果数据。 在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

公开(公告)号：US20080294413A1

公开(公告)日：2008-11-27

申请号：US12130104

申请日：2008-05-30

申请人： GABOR BOBOK ,  Wolfgang Roesner ,  Derek E. Williams

发明人： GABOR BOBOK ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。

公开(公告)号：US07453759B2

公开(公告)日：2008-11-18

申请号：US11380257

申请日：2006-04-26

申请人： Yee Ja ,  Bradley S. Nelson ,  Wolfgang Roesner

发明人： Yee Ja ,  Bradley S. Nelson ,  Wolfgang Roesner

IPC分类号： G11C8/00

CPC分类号： G06F17/504 ,  G06F17/5022 ,  G06F2217/62

摘要： Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.

摘要翻译： 电路的异步行为是通过修改网表中的锁存器来增加锁存器的额外端口来建模的，例如，单端口锁存器被转换成双端口锁存器。 每个输入端口都有一个使能线和数据输入。 添加端口中输入的数据是来自锁存器输出的反馈线，加入端口中的使能线为所有原始使能线的逻辑或。 通过在更高级别的模型中添加这个额外的锁存端口，可以引入断言逻辑，以确保给定锁存器中的一个和唯一一个锁存端口在同一仿真周期内始终处于活动状态。 然后可以在设计方法之前对该模型进行测试，然后才能获得后合成网表。 该模型也可用于模拟和正式或半正式验证。

公开(公告)号：US07373290B2

公开(公告)日：2008-05-13

申请号：US10388976

申请日：2003-03-13

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F9/44

CPC分类号： G06F17/5022

摘要： Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possible keyword/value pairs sets for which result data can be obtained, and the restriction list specifies a fewer number of keyword/value pair sets for which the result data can be queried based upon at least one keyword. In response to receipt of result data obtained by simulation of the HDL model, the result data are stored within a data storage subsystem by reference to the restriction list, such that particular result data attributable to each of the plurality of keyword/value sets is separately accessible.

摘要翻译： 本文公开了一种基于关键字来管理硬件描述语言（HDL）模型的模拟处理的数据结果的方法。 根据该方法，接收与HDL模型相关联的限制列表。 HDL模型具有可以获得结果数据的可能的关键字/值对集合的最大数量，并且限制列表指定少量关键字/值对集合，根据至少一个关键字可以查询结果数据 。 响应于接收到通过HDL模型的模拟而获得的结果数据，结果数据通过参考限制表被存储在数据存储子系统内，使得归因于多个关键字/值集合中的每一个的特定结果数据是分开的 无障碍。

公开(公告)号：US07359847B2

公开(公告)日：2008-04-15

申请号：US09997460

申请日：2001-11-30

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06G7/62 ,  G06F9/44 ,  G06F13/10 ,  G06F13/12

CPC分类号： G06F17/5022

摘要： A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received by the instrumentation server from one or more simulation clients. A first and a second counter report are generated for the hardware simulation model, in which the first and second counter reports are derived from the count event data received by the instrumentation server. The first counter report is compared to the second counter report, and responsive to this comparison, a counter difference report is generated within the instrumentation server that conveys count event trends associated with the simulation model under different simulation testcases.

摘要翻译： 一种方法和系统，用于通过测试包含模拟客户端和仪器服务器的批量模拟场内的硬件仿真模型来提供集中访问计数事件信息。 所述硬件仿真模型的计数事件数据由仪器服务器从一个或多个仿真客户端接收。 为硬件仿真模型生成第一和第二计数器报告，其中第一和第二计数器报告是从由仪器服务器接收的计数事件数据导出的。 将第一个计数器报告与第二个计数器报告进行比较，并根据此比较，在仪表服务器内生成一个反差异报告，传达与不同模拟测试用例下的仿真模型相关的计数事件趋势。

公开(公告)号：US20080040695A1

公开(公告)日：2008-02-14

申请号：US11874620

申请日：2007-10-18

申请人： Bing-Lun Chu ,  Yee Ja ,  Bradley Nelson ,  Wolfgang Roesner

发明人： Bing-Lun Chu ,  Yee Ja ,  Bradley Nelson ,  Wolfgang Roesner

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5031

摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

摘要翻译： 提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。 利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。 这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或故障危险以及基本逻辑元件的输入是否可以基于切换 或异步接口逻辑中另一原始逻辑元件的故障危险。 这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。 然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

公开(公告)号：US20080021691A1

公开(公告)日：2008-01-24

申请号：US11829447

申请日：2007-07-27

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance containing a latch that is represented by a particular design graphical representation. A configuration entity instance associated with the particular design entity is identified within a configuration database associated with the simulated system. The configuration entity instance has a plurality of different settings that each reflects a value of the latch. Within the display device, a configuration graphical representation of the configuration entity instance is presented in association with the particular design graphical representation corresponding to the particular design entity instance. In addition, a current setting of the configuration entity instance is presented concurrently with the configuration graphical representation.

摘要翻译： 在显示装置内，为模拟系统内的多个分层布置的设计实体实例中的每一个显示多个设计图形表示中的相应一个。 设计实体实例包括包含由特定设计图形表示表示的锁存器的特定设计实体实例。 在与模拟系统相关联的配置数据库中识别与特定设计实体相关联的配置实体实例。 配置实体实例具有多个不同的设置，每个设置反映锁存器的值。 在显示设备内，与对应于特定设计实体实例的特定设计图形表示相关联地呈现配置实体实例的配置图形表示。 此外，配置实体实例的当前设置与配置图形表示同时呈现。

公开(公告)号：US07305639B2

公开(公告)日：2007-12-04

申请号：US11055863

申请日：2005-02-11

申请人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

发明人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

摘要翻译： 提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。 提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。 然后提供第一验证机制以验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。 提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。 提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。

公开(公告)号：US20070174806A1

公开(公告)日：2007-07-26

申请号：US11408835

申请日：2006-04-21

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

摘要翻译： 公开了一种将映射函数与由一个或多个硬件描述语言（HDL）文件定义的数字设计的配置结构相关联的方法。 根据该方法，在HDL文件中，在形成数字设计的至少一部分的设计实体内指定配置锁存器。 此外，指定了一个Dial，其定义了多个输入值中的每一个与多个不同输出值中的相应的一个之间的关系。 HDL文件还包括一个语句，用于与配置锁存器相关联地实例化Dial的实例，使得在配置锁存器中包含的值与Dial的实例的输入值之间存在一一对应的对应关系。 HDL文件还包括将Dial与将映射功能相关联的语句，该映射函数将选择的变换应用于从Dial的实例读取或写入的值。

公开(公告)号：US07213225B2

公开(公告)日：2007-05-01

申请号：US10857461

申请日：2004-05-28

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/505

摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。