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1.发明授权Program product providing a configuration specification language having clone latch support 有权提供具有克隆锁存器支持的配置规范语言的程序产品公开(公告)号：US08028273B2
公开(公告)日：2011-09-27
申请号：US12106053
申请日：2008-04-18
CPC分类号： G06F17/5045 , G06F17/5022
摘要： Methods, data processing systems, and program products supporting the insertion of clone latches within a digital design are disclosed. According to one method, a parent latch within the digital design is specified in an HDL statement in one of the HDL files representing a digital design. In addition, a clone latch is specified within the digital design utilizing an HDL clone latch declaration. An HDL attribute-value pair is associated with the HDL clone latch declaration to indicate a relationship between the clone latch and the parent latch according to which the clone latch is automatically set to a same value as the parent latch when the parent latch is set. Thereafter, when a configuration compiler receives one or more design intermediate files containing the clone latch declaration, the configuration compiler creates at least one data structure in a configuration database representing the clone latch and the relationship between the clone latch and the parent latch.
摘要翻译： 公开了支持在数字设计中插入克隆锁存器的方法，数据处理系统和程序产品。 根据一种方法，数字设计中的父锁存器在表示数字设计的HDL文件之一中的HDL语句中被指定。 此外，使用HDL克隆锁存器声明在数字设计中指定克隆锁存器。 HDL属性值对与HDL克隆锁存器声明相关联，以指示克隆锁存器和父锁存器之间的关系，根据该关系，克隆锁存器在父锁存器被置位时自动设置为与父锁存器相同的值。 此后，当配置编译器接收到包含克隆锁存器声明的一个或多个设计中间文件时，配置编译器在表示克隆锁存器的配置数据库中创建至少一个数据结构以及克隆锁存器和父锁存器之间的关系。
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公开(公告)号：US07840758B2
公开(公告)日：2010-11-23
申请号：US11689990
申请日：2007-03-22
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。
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3.发明授权Program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language 失效使用高级语言定义和记录模拟的最小和最大事件计数的程序产品公开(公告)号：US07529655B2
公开(公告)日：2009-05-05
申请号：US12106416
申请日：2008-04-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.
摘要翻译： 根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。 在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。 然后接收并处理从模拟设计获得的仿真结果数据。 在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。
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4.发明授权Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response 有权链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问公开(公告)号：US07409504B2
公开(公告)日：2008-08-05
申请号：US11245312
申请日：2005-10-06
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
摘要翻译： 一种用于在数据在第一耦合处理器的高速缓存中接收数据之前顺序耦合高速缓存行的连续处理器请求的方法。 同质和非均匀的操作彼此链接，并且一致性协议包括与链接状态相关联的几个新的中间一致性响应。 分配链接一致性状态以在第一处理器接收到数据之前跟踪处理器请求链和授予访问权限。 链接的一致性状态还标识接收处理器的地址。 当在链中的第一处理器的高速缓存处接收到数据时，处理器完成其对数据的（或与）数据的操作，然后将数据转发到链中的下一个处理器。 链接的一致性协议通过减少重试次数来释放地址总线带宽。
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5.发明授权Method and system for reducing storage requirements of simulation data via keyword restrictions 有权通过关键词限制减少模拟数据存储需求的方法和系统公开(公告)号：US07373290B2
公开(公告)日：2008-05-13
申请号：US10388976
申请日：2003-03-13
IPC分类号： G06F9/44
CPC分类号： G06F17/5022
摘要： Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possible keyword/value pairs sets for which result data can be obtained, and the restriction list specifies a fewer number of keyword/value pair sets for which the result data can be queried based upon at least one keyword. In response to receipt of result data obtained by simulation of the HDL model, the result data are stored within a data storage subsystem by reference to the restriction list, such that particular result data attributable to each of the plurality of keyword/value sets is separately accessible.
摘要翻译： 本文公开了一种基于关键字来管理硬件描述语言（HDL）模型的模拟处理的数据结果的方法。 根据该方法，接收与HDL模型相关联的限制列表。 HDL模型具有可以获得结果数据的可能的关键字/值对集合的最大数量，并且限制列表指定少量关键字/值对集合，根据至少一个关键字可以查询结果数据 。 响应于接收到通过HDL模型的模拟而获得的结果数据，结果数据通过参考限制表被存储在数据存储子系统内，使得归因于多个关键字/值集合中的每一个的特定结果数据是分开的 无障碍。
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6.发明授权Method for priority scheduling and priority dispatching of store conditional operations in a store queue 有权存储条件操作在存储队列中的优先级调度和优先级调度的方法公开(公告)号：US07360041B2
公开(公告)日：2008-04-15
申请号：US10970437
申请日：2004-10-21
IPC分类号： G06F12/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译： 一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。 向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。 每当在条目中放置STCX操作时，优先级位置位。 在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。 具有优先级位的条目在架构规则中的选择过程中被赋予优先级。 然后在既定规则内尽可能早地选择该条目进行发送。
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公开(公告)号：US07359847B2
公开(公告)日：2008-04-15
申请号：US09997460
申请日：2001-11-30
CPC分类号： G06F17/5022
摘要： A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received by the instrumentation server from one or more simulation clients. A first and a second counter report are generated for the hardware simulation model, in which the first and second counter reports are derived from the count event data received by the instrumentation server. The first counter report is compared to the second counter report, and responsive to this comparison, a counter difference report is generated within the instrumentation server that conveys count event trends associated with the simulation model under different simulation testcases.
摘要翻译： 一种方法和系统，用于通过测试包含模拟客户端和仪器服务器的批量模拟场内的硬件仿真模型来提供集中访问计数事件信息。 所述硬件仿真模型的计数事件数据由仪器服务器从一个或多个仿真客户端接收。 为硬件仿真模型生成第一和第二计数器报告，其中第一和第二计数器报告是从由仪器服务器接收的计数事件数据导出的。 将第一个计数器报告与第二个计数器报告进行比较，并根据此比较，在仪表服务器内生成一个反差异报告，传达与不同模拟测试用例下的仿真模型相关的计数事件趋势。
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8.发明授权Processor, data processing system and method for synchronizing access to data in shared memory 有权处理器，数据处理系统和方法，用于同步共享存储器中数据的访问公开(公告)号：US07228385B2
公开(公告)日：2007-06-05
申请号：US10965113
申请日：2004-10-14
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3851 , G06F12/0811 , G06F12/0831 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，至少一个执行存储条件指令以确定存储目标地址的指令执行单元，存储器 在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。 定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行 加载预备操作先前绑定到的高级缓存。
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9.发明授权High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system 失效适用于多处理器数据处理系统锁定采集的高速推广机制公开(公告)号：US07213248B2
公开(公告)日：2007-05-01
申请号：US10268729
申请日：2002-10-10
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
摘要翻译： 多处理器数据处理系统包括耦合到互连的多个处理器和包含至少一个促销位字段的全局推广设备。 第一处理器执行包括负载型指令的高速指令序列，以在除了至少第二处理器之外的全局促进设备中获取促销位字段。 所述请求可以被耦合到互连的所有处理器可见。 响应于负载型指令的执行，第一处理器的寄存器接收指示通过执行负载型指令是否获取了促销位字段的寄存器位字段。 虽然第一处理器保持不属于第二处理器的升级位字段，但允许第二处理器在互连上发起请求。 优选地，促销比特字段与数据分开处理，并且促销比特字段的通信不需要数据高速缓存行的移动。
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10.发明授权Method, system and program product for specifying and using register entities to configure a simulated or physical digital system 失效用于指定和使用寄存器实体配置模拟或物理数字系统的方法，系统和程序产品公开(公告)号：US07213225B2
公开(公告)日：2007-05-01
申请号：US10857461
申请日：2004-05-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.
摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。
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