公开(公告)号：US07944724B2

公开(公告)日：2011-05-17

申请号：US12431332

申请日：2009-04-28

Applicant: Scott Chu

Inventor： Scott Chu

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced.

Abstract translation: 一列三元内容可寻址存储器（TCAM）单元包括在列的中心处或附近的位置处扭曲的位线对。 将数据写入（并从其读取）位于扭转位置上方的TCAM单元，具有第一位线极性。 数据被写入位于扭转位置下方的TCAM单元，具有第二位线极性，与第一位线极性相反。 结果，减少了存储“不关心”值的TCAM单元引入的读出漏电流。

公开(公告)号：US07936577B1

公开(公告)日：2011-05-03

申请号：US12964712

申请日：2010-12-09

Applicant: Martin Fabry

Inventor： Martin Fabry

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) may include a plurality of precharge circuits, each coupled to a group of CAM cells and comprising a first precharge path that is temporarily enabled in response to an activated first control signal, and a second precharge path that is temporarily enabled in response to an activated second control signal and a valid indication that indicates whether or not the corresponding group of CAM cells stores valid data, the valid indication being different than the first and second control signals.

Abstract translation: 内容可寻址存储器（CAM）可以包括多个预充电电路，每个预充电电路耦合到一组CAM单元，并且包括响应于激活的第一控制信号临时使能的第一预充电路径和临时地启动的第二预充电路径 响应于激活的第二控制信号和指示对应的CAM单元组是否存储有效数据的有效指示被启用，该有效指示不同于第一和第二控制信号。

公开(公告)号：US07924828B2

公开(公告)日：2011-04-12

申请号：US10930455

申请日：2004-08-31

Applicant: David T. Hass ,  Abbas Rashid

Inventor： David T. Hass ,  Abbas Rashid

IPC: H04L12/56

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07919957B2

公开(公告)日：2011-04-05

申请号：US12723538

申请日：2010-03-12

Applicant: Shwetabh Verma ,  Marc Loinaz

Inventor： Shwetabh Verma ,  Marc Loinaz

IPC: G05F1/40

CPC classification number: G05F1/575

Abstract: A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator generates, during a clock cycle, a binary output based on a comparison between reference and operating voltages. The finite state machine (FSM) is coupled to receive at least one control signal that indicates a target operating state for the digital linear voltage regulator. The FSM receives the binary output from the comparator and generates a digital word, during a clock cycle, based on the target operating state of the digital linear voltage regulator and on the binary output. The current DAC is coupled to the FSM, receives the digital word and delivers current at the desired voltage to the dynamic load.

Abstract translation: 数字线性稳压器包括比较器，有限状态机和当前的数模转换器（DAC）。 优选地，比较器被耦合以接收提供给动态负载的参考电压和工作电压。 比较器根据参考电压和工作电压之间的比较，在时钟周期内产生二进制输出。 有限状态机（FSM）被耦合以接收指示数字线性电压调节器的目标操作状态的至少一个控制信号。 FSM从比较器接收二进制输出，并在时钟周期内根据数字线性稳压器的目标工作状态和二进制输出产生数字字。 当前的DAC耦合到FSM，接收数字字，并将电流以期望的电压传递给动态负载。

公开(公告)号：US07911818B2

公开(公告)日：2011-03-22

申请号：US12405000

申请日：2009-03-16

Applicant: Scott Chu

Inventor： Scott Chu

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair.

Abstract translation: CAM列结构包括经由搜索线对将搜索数据驱动到多个CAM单元的接口。 CAM单元分为多个部分，每个部分包括：一组CAM单元，耦合到该组CAM单元的位线对，耦合到位线对的读出放大器，配置成驱动读取的三态读缓冲器 从读出放大器到搜索线对的数据，以及一对三态写入缓冲器，被配置为驱动从搜索线对到位线对的写入数据。 在一个实施例中，一对三态写缓冲器由耦合到检测放大器的搜索线对的一对开关代替。 搜索线对可以由三态缓冲器分段，三态缓冲器被控制以驱动搜索线对的搜索，读取和写入数据。

公开(公告)号：US07907432B2

公开(公告)日：2011-03-15

申请号：US12495202

申请日：2009-06-30

Applicant: Chetan Deshpande ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Chetan Deshpande ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows.

Abstract translation: CAM设备包括耦合到可编程优先级编码（PPE）逻辑电路的CAM阵列。 CAM阵列同时将多个输入数据与存储的数据进行比较，以产生提供给PPE逻辑电路的相应匹配结果。 PPE逻辑电路响应于可以切换以交替地选择各种流的匹配结果的流选择信号，选择性地有利于所选流量的匹配结果与其他流的匹配结果。 以这种方式，即使所选流的HPM索引的优先级低于非选择流的HPM索引，也可以生成并输出所选流的匹配结果，从而确保不同流之间的匹配结果报告的均匀分布 。

公开(公告)号：US07904643B1

公开(公告)日：2011-03-08

申请号：US12732515

申请日：2010-03-26

Applicant: Srinivasan Venkatachary

Inventor： Srinivasan Venkatachary

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device, method, and method of generating entries for range matching are disclosed. A CAM device (800) according to one embodiment can include a pre-encoder (806) that encodes range bit values W into additional bits E. Additional bits E can indicate compression of range rules according to particular bit pairs. A CAM array (802) can include entries that store compressed range code values (RANGE) with corresponding additional bit values (ENC). Alternate embodiments can include pre-encoders that encode portions of range values (K1 to Ki) in a “one-hot” fashion. Corresponding CAM entries can include encoded value having sections that each represent increasingly finer divisions of a range space.

Abstract translation: 公开了一种内容可寻址存储器（CAM）装置，方法和用于生成范围匹配的条目的方法。 根据一个实施例的CAM设备（800）可以包括将范围位值W编码为附加位E的预编码器（806）。附加位E可以指示根据特定位对的范围规则的压缩。 CAM阵列（802）可以包括存储具有相应附加位值（ENC）的压缩范围代码值（RANGE）的条目。 替代实施例可以包括以“一热”方式编码范围值（K1至Ki）的部分的预编码器。 相应的CAM条目可以包括具有每个表示范围空间越来越精细的部分的部分的编码值。

公开(公告)号：US07893858B2

公开(公告)日：2011-02-22

申请号：US12398926

申请日：2009-03-05

Applicant: Pirooz Hojabri ,  Jack Lam

Inventor： Pirooz Hojabri ,  Jack Lam

IPC: H03M1/34

CPC classification number: H03M1/141

Abstract: A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.

Abstract translation: 一种用于进行流水线电容折叠和插值模数转换的方法和装置。 在一个实施例中，该装置包括多级流水线模数转换器，其具有分布式采样/保持和前置放大器，折叠和内插单元，其使用电容性折叠和电容插值组合多个预放大信号; 以及解码单元，其被耦合以对来自折叠和插值单元的输出信号进行解码。 分布式采样/保持和前置放大器大大提高了输入动态范围，从而提高了ADC的全线性。 这种技术在每个采样中提供了固有的动态偏移消除，可以使用核心数字电源在亚微米CMOS中实现。

公开(公告)号：US07889582B1

公开(公告)日：2011-02-15

申请号：US12046675

申请日：2008-03-12

Applicant: Steven Butler

Inventor： Steven Butler

IPC: G11C7/00

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory device is provided for performing writing operations on memory cells while maintaining a stability thereof. A memory array is provided including a plurality of memory cells. Additionally, segmented write bitlines are provided for performing writing operations on the memory cells while maintaining a stability thereof.

Abstract translation: 提供了一种存储器件，用于在保持其稳定性的同时对存储器单元执行写入操作。 提供了包括多个存储单元的存储器阵列。 此外，提供分段写入位线，用于在保持其稳定性的同时对存储器单元执行写入操作。

公开(公告)号：US20110013643A1

公开(公告)日：2011-01-20

申请号：US12890551

申请日：2010-09-24

Applicant: Brian Hang Wai Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

Inventor： Brian Hang Wai Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

IPC: H04L12/56

CPC classification number: H04L49/25 ,  H04L49/101 ,  H04L49/3027 ,  H04L49/3045

Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position.

Abstract translation: 本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 本发明还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。本发明进一步 包括被配置为在历元期间接收所述一组分组的一部分的输出终端，所述仲裁器电路被配置为在所述时期期间迭代地扫描所述矩阵，并向所述虚拟输出队列发出所述一组授权信号以确定哪些服务请求被授权， 以及仲裁器控制器，被配置为使用非冲突矩阵元素的阵列启动仲裁器电路。 由此，仲裁器电路在第一纪元期间扫描矩阵，发出授权信号集合，允许一组授权的服务请求基本上完成，并且如果需要，在随后的时期期间扫描矩阵。 本发明还涉及一种交叉开关控制器，其包括耦合到输入端和矩阵电路的仲裁预处理器，并且被配置为以映射矩阵的形式表示该组服务请求信号，并且还被配置为将第一 部分地基于映射算法将服务请求信号的映射位置映射到第二映射位置。 本发明还包括耦合到输出端和矩阵电路的仲裁后处理器，还被配置为将服务请求信号的第二映射位置转换回第一映射位置。