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667 条记录 (耗时 0.015 秒)

    Apparatus for changing the information recorded on cards
    111.
    发明授权
    Apparatus for changing the information recorded on cards 失效
    更改记录在卡上的信息的装置

    公开(公告)号：US3560715A

    公开(公告)日：1971-02-02

    申请号：US3560715D

    申请日：1967-05-29

    申请人： OMRON TATEISI ELECTRONICS CO

    发明人： AKAMATSU HIROO ,  NAGATA MASANORI

    IPC分类号： G07F7/02 ,  G06K5/02

    CPC分类号： G07F7/02 ,  G06Q20/3437

    摘要： An apparatus for changing the information recorded on cards and especially the monetary value given to cards used in place of coins and/or bills in automatic vending machines and the like. The monetary value of a card as represented by code markings thereon is first read and memorized. Upon selection of an article the monetary value assigned thereto is subtracted from the memorized value read from the card. The result of the subtraction is recorded on the card for future use in place of the original monetary value recorded on the card. Dispensing of articles having a value greater than the memorized value is prevented. System and detailed circuit diagrams are provided.

    Monitor circuit for detecting noise conditions through input output coincidence comparison
    119.
    发明授权
    Monitor circuit for detecting noise conditions through input output coincidence comparison 失效
    监控电路通过输入输出一致比较检测噪声条件

    公开(公告)号：US5263170A

    公开(公告)日：1993-11-16

    申请号：US532169

    申请日：1990-06-01

    申请人： Yukio Kato

    发明人： Yukio Kato

    IPC分类号： G05B19/05 ,  G06F11/00 ,  G06F11/277 ,  G06F11/30

    CPC分类号： G06F11/0763 ,  G05B19/058 ,  G05B2219/1194 ,  G05B2219/1199 ,  G06F11/277

    摘要： A monitor circuit is provided, which includes a data storage unit having dummy data stored therein, a buffer circuit connected to the output of the data storage unit, a coincidence circuit for comparing the data on the I/O bus connected between the buffer circuit and I/O units with the dummy data of the data storage unit, and a flag circuit for setting an abnormal flag responsive to the non-coincidence output from the coincidence circuit. During the I/O refresh of a PC, such an abnormal flag is set in response to a disturbance of the I/O bus. The I/O refresh is repeatedly performed in the event the flag is set.

    摘要翻译： 提供了一种监视器电路，其包括具有存储在其中的虚拟数据的数据存储单元，连接到数据存储单元的输出的缓冲电路，用于比较连接在缓冲电路与缓冲电路之间的I / O总线上的数据的符合电路 具有数据存储单元的伪数据的I / O单元，以及响应于从符合电路的不一致输出而设置异常标志的标志电路。 在PC的I / O刷新期间，响应于I / O总线的干扰而设置这样的异常标志。 在设置标志的情况下，重复执行I / O刷新。

    Reasoning computer system
    120.
    发明授权
    Reasoning computer system 失效
    推理电脑系统

    公开(公告)号：US5249258A

    公开(公告)日：1993-09-28

    申请号：US865628

    申请日：1992-04-09

    申请人： Atsushi Hisano

    发明人： Atsushi Hisano

    IPC分类号： G06N7/04

    CPC分类号： G06N7/04 ,  Y10S706/90

    摘要： A fuzzy reasoning computer having a multi-stage construction is disclosed which includes a primary fuzzy reasoning computer at a rank having a reasoning system for producing a reasoned result, at least one child fuzzy reasoning computer at a lower rank having a reasoning system for producing a reasoning result and a system for providing the reasoning results of the at least one child fuzzy reasoning computer to the reasoning system of the primary fuzzy reasoning computer in such a manner that the reasoning performed by the primary fuzzy reasoning computer is assisted by the at least one child fuzzy reasoning computer.

    摘要翻译： 公开了一种具有多级结构的模糊推理计算机，其包括具有用于产生推理结果的推理系统的初级模糊推理计算机，具有用于产生推理结果的推理系统的至少一个儿童模糊推理计算机具有用于产生推理结果的推理系统 推理结果和用于将所述至少一个儿童模糊推理计算机的推理结果提供给所述主要模糊推理计算机的推理系统的系统，使得由所述主要模糊推理计算机执行的推理由所述至少一个 儿童模糊推理计算机。