公开(公告)号：US20240118992A1

公开(公告)日：2024-04-11

申请号：US18487490

申请日：2023-10-16

Applicant: Intel Corporation

Inventor： Martin-Thomas Grymel ,  David Bernard ,  Martin Power ,  Niall Hanrahan ,  Kevin Brady

IPC: G06F11/36 ,  G06F11/277 ,  G06F11/30 ,  G06N3/04

CPC classification number: G06F11/3652 ,  G06F11/277 ,  G06F11/3075 ,  G06F11/3656 ,  G06N3/04

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

公开(公告)号：US20180260297A1

公开(公告)日：2018-09-13

申请号：US15455619

申请日：2017-03-10

Applicant: Artesyn Embedded Computing, Inc.

Inventor： Gary PERKINS ,  Malcolm J. RUSH ,  Andrew PORTER

IPC: G06F11/34 ,  H04L29/06 ,  G06F11/30

CPC classification number: G06F11/3409 ,  G06F11/0739 ,  G06F11/0796 ,  G06F11/277 ,  G06F11/3013 ,  G06F11/3495 ,  H04L67/12 ,  H04L69/22 ,  H04L69/40

Abstract: A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.

公开(公告)号：US20180246796A1

公开(公告)日：2018-08-30

申请号：US15442039

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu

IPC: G06F11/277 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  G11C29/32 ,  G11C29/38 ,  G06F11/22

CPC classification number: G06F11/277 ,  G06F11/221 ,  G06F11/2221 ,  G06F13/1668 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/38

Abstract: Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.

公开(公告)号：US09990212B2

公开(公告)日：2018-06-05

申请号：US14360657

申请日：2013-02-19

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Ezekiel Kruglick

IPC: G06F9/44 ,  G06F11/34 ,  G06F11/30 ,  G01R31/3185 ,  G06F11/277 ,  G06F9/445

CPC classification number: G06F9/44505 ,  G01R31/318519 ,  G06F11/277 ,  G06F11/3024 ,  G06F11/3409

Abstract: Techniques described herein generally include methods for the testing and repair of a hardware accelerator image in a programmable logic circuit. In a processor chip that includes multiple programmable logic circuits, a hardware accelerator image programmed into a first programmable logic circuit is tested by programming a testing circuit with a duplicate hardware accelerator image and bringing the testing circuit to the same logic state as the first programmable logic circuit. Comparing outputs from the first programmable logic circuit and the testing circuit indicates the accuracy of the hardware accelerator image programmed into the first programmable logic circuit. The testing circuit may replace the first programmable logic circuit, or the testing circuit may be reprogrammed for testing other hardware accelerator images programmed into other programmable logic circuits of the processor chip.

公开(公告)号：US09983938B2

公开(公告)日：2018-05-29

申请号：US14752802

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Stephen F. Heil ,  Sitaram V. Lanka ,  Adrian M. Caulfield ,  Eric S. Chung ,  Andrew R. Putnam ,  Douglas C. Burger ,  Yi Xiao

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/50 ,  G06F11/07 ,  G06F11/277

CPC classification number: G06F11/1441 ,  G06F9/5027 ,  G06F9/5061 ,  G06F11/0709 ,  G06F11/0724 ,  G06F11/0793 ,  G06F11/277 ,  G06F2201/805

Abstract: Aspects extend to methods, systems, and computer program products for locally restoring functionality at acceleration components. A role can be locally restored at an acceleration component when an error is self-detected at the acceleration component (e.g., by local monitoring logic). Locally restoring a role can include resetting internal state (application logic) of the acceleration component providing the role. Self-detection of errors and local restoration of a role is less resource intensive and more efficient than using external components (e.g., high-level services) to restore functionality at an acceleration component and/or to reset an entire graph. Monitoring logic at multiple acceleration components can locally reset roles in parallel to restore legitimate behavior of a graph.

公开(公告)号：US09753825B2

公开(公告)日：2017-09-05

申请号：US14617526

申请日：2015-02-09

Applicant: Oracle International Corporation

Inventor： Guan Nan He ,  Ying Xi

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/273 ,  G06F11/277

CPC classification number: G06F11/263 ,  G06F11/273 ,  G06F11/277

Abstract: Systems and methods can use a testing framework for testing an event processing system. The testing framework operates to send one or more input events in an event stream to an event processing system, wherein each said input event is associated with a timestamp. Also, the testing framework can receive one or more actual output events from the event processing system, wherein each said actual output event is associated with a timestamp. Furthermore, the testing framework can compare said one or more actual output events in an event window with one or more expected output events for the event window.

公开(公告)号：US09639076B2

公开(公告)日：2017-05-02

申请号：US14566046

申请日：2014-12-10

Applicant: FUJITSU LIMITED

Inventor： Takashi Miyoshi

IPC: G06F11/00 ,  G05B15/02 ,  G06F11/34 ,  G06F11/22 ,  G06F11/277

CPC classification number: G05B15/02 ,  G06F11/22 ,  G06F11/2221 ,  G06F11/27 ,  G06F11/277 ,  G06F11/34

Abstract: A switch apparatus for connecting an arithmetic processing apparatus and a control apparatus that controls the processing apparatus to an I/O apparatus is disclosed, the switch apparatus includes: a switch unit that connects either the processing apparatus or the control apparatus to the I/O; a first input/output control unit that outputs a first command that is received from the processing apparatus to the I/O through the switch unit, receives a response from the I/O that is operated based on the first command, through the switch unit, and outputs the received response to the processing apparatus; and a second input/output control unit that outputs a second command that is received from the control apparatus, to the I/O through the switch unit, receives a test result of the I/O that is tested based on the second command, through the switch unit, and outputs the received test result to the control apparatus.

公开(公告)号：US20160328281A1

公开(公告)日：2016-11-10

申请号：US15109429

申请日：2014-12-10

Applicant: ENTRIX Co., Ltd.

Inventor： Dong-su LEE ,  Dong-gook KIM

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0709 ,  G06F11/0712 ,  G06F11/0751 ,  G06F11/277 ,  G06F11/324

Abstract: The present invention relates to an application error detection method for a cloud streaming service, and an apparatus and a system therefor. According to the present invention, with respect to an application executed in a streaming server, it is possible to detect an application error by determining whether a reference image coincides with an execution screen of the application.

Abstract translation: 本发明涉及云流服务的应用错误检测方法及其装置及系统。 根据本发明，对于在流服务器中执行的应用，可以通过确定参考图像是否与应用的执行屏幕一致来检测应用错误。

公开(公告)号：US09310436B2

公开(公告)日：2016-04-12

申请号：US14166383

申请日：2014-01-28

Applicant: OmniVision Technologies, Inc.

Inventor： Jenny Picalausa ,  Kristoffer Koch

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/277 ,  G01R31/3193 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3181 ,  G06F13/24 ,  G06F11/26 ,  H04L12/26

CPC classification number: G01R31/318544 ,  G01R31/31703 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/3187 ,  G01R31/31932 ,  G01R31/31935 ,  G06F11/2236 ,  G06F11/261 ,  G06F11/277 ,  G06F13/24 ,  H04L43/50

Abstract: A system has in an integrated circuit a seed memory coupled to seed a vector generator that provides a vector to at least one scan chain of a first functional unit. A signature generator is configured to generate a signature from scan chain data, the signature is compared to an expected signature in a signature memory. A state memorizer is provided for saving a state of the functional unit and to restore the state of the functional unit as testing is completed. The system also has apparatus configured to determine an idle condition of the functional unit despite a non-idle state of the system; and a control unit configured to operate a test sequence when the functional unit is idle, the test sequence saving a state of the unit, generating vectors and signatures and verifying the signatures, and restoring the state of the unit.

Abstract translation: 一种系统在集成电路中具有耦合到种子矢量发生器的种子存储器，其向第一功能单元的至少一个扫描链提供向量。 签名生成器被配置为从扫描链数据生成签名，将签名与签名存储器中的预期签名进行比较。 提供状态存储器，用于保存功能单元的状态，并在测试完成时恢复功能单元的状态。 该系统还具有被配置为尽管系统的非空闲状态来确定功能单元的空闲状态的装置; 以及控制单元，被配置为当所述功能单元空闲时操作测试序列，所述测试序列保存所述单元的状态，生成向量和签名并验证所述签名，以及恢复所述单元的状态。

公开(公告)号：US09287877B2

公开(公告)日：2016-03-15

申请号：US14375761

申请日：2013-02-14

Applicant: TAIYO YUDEN CO., LTD.

Inventor： Masayuki Satou ,  Koshi Sato

IPC: H03K19/00 ,  H03K19/177 ,  G06F11/277 ,  H03K19/003

CPC classification number: H03K19/17728 ,  G06F11/277 ,  H03K19/003 ,  H03K19/17732 ,  H03K19/1776

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in accordance with an operation switch signal.

Abstract translation: 一种能够重构的半导体器件，包括：配置阵列并彼此连接的多个逻辑单元，其中每个逻辑单元包括一对第一和第二存储单元单元，第一和第二存储器中的每一个 当真值表数据被写入时，单元单元作为逻辑元件操作，其被配置为使得由多个地址指定的输入值的逻辑计算被输出到数据线，和/或作为连接元件操作， 写入真值表数据，其被配置为使得由特定地址指定的输入值被输出到要连接到另一存储单元单元的地址的数据线，第一存储单元单元的后级包括 与时钟同步的顺序电路，并且对于每对第一和第二存储单元单元，逻辑单元包括选择单元，其选择性地向第一或第二存储器输出地址 d个存储单元单元。