Abstract:
A lock-based software transactional memory (STM) implementation may determine whether a transaction's write-set is static (e.g., known in advance not to change). If so, and if the read-set is not static, the STM implementation may execute, or attempt to execute, the transaction as a semi-static transaction. A semi-static transaction may involve obtaining, possibly after incrementing, a reference version value against which to subsequently validate that memory locations, such as read-set locations, have not been modified concurrently with the semi-static transaction. The read-set locations may be validated while locks are held for the locations to be written (e.g., the write-set locations). After committing the modifications to the write-set locations and as part of releasing the locks, versioned write-locks associated with the write-set locations may be updated to reflect the previously obtained, or newly incremented, reference version value.
Abstract:
A Scalable NonZero Indicator (SNZI) object in a concurrent computing application may include a shared data portion (e.g., a counter portion) and a shared nonzero indicator portion, and/or may be an element in a hierarchy of SNZI objects that filters changes in non-root nodes to a root node. SNZI objects may be accessed by software applications through an API that includes a query operation to return the value of the nonzero indicator, and arrive (increment) and depart (decrement) operations. Modifications of the data portion and/or the indicator portion may be performed using atomic read-modify-write type operations. Some SNZI objects may support a reset operation. A shared data object may be set to an intermediate value, or an announce bit may be set, to indicate that a modification is in progress that affects its corresponding indicator value. Another process or thread seeing this indication may “help” complete the modification before proceeding.
Abstract:
A system that executes a long transaction in a system with limited transactional hardware resources. During operation, the system executes the long transaction in a non transactional mode, which does not use transactional hardware resources. The system defers stores generated during the long transaction so that the stores are not committed to the architectural state of a processor until the transaction is successfully completed. If the long transaction successfully completes, the system commits the long transaction, which involves performing multiple hardware transactions to commit the deferred stores to the architectural state of the processor.
Abstract:
A computer system includes multiple processing threads that execute in parallel. The multiple processing threads have access to a global environment including i) shared data utilized by the multiple processing threads, ii) a globally accessible register or buffer of version information that changes each time a respective one of the multiple processing threads modifies the shared data, and iii) respective lock information indicating whether one of the multiple processing threads has locked the shared data preventing other processing threads from modifying the shared data. To prevent data corruption, each of the processing threads aborts if a given processing thread detects a change in the version information or another processing thread has a lock on the shared data. This technique is well suited for use in applications such as processing threads that support a high number of reads with a corresponding number of fewer respective writes to shared data.
Abstract:
In a multi-processor multi-threaded computer system, resources are dynamically assigned during program operation to either threads or processors in such a manner that resource usage is maximized. In one embodiment, the choice of whether to assign resources to threads or processors is dependent on the number of threads versus the number of processors. In another embodiment, when the system is operating in one assignment mode, the amount of wasted resources is measured and when this measured amount exceeds a predetermined threshold based on the maximum resources that could be wasted were the system operating in the other assignment mode, the assignment is switched to the other assignment mode.
Abstract:
A communication system includes communication devices which communicate during a communication session. During communication session establishment, the devices exchange a session key in an encrypted manner for privacy. When one device has information to transfer to the other device, the one device will append the session key to the information and apply a hash function thereto to generate a hash value, and generate a message packet for transfer to the other device that includes an information portion containing the information and a hash value portion containing the hash value. When the other device receives the message packet, it will append the session key to the information from the information portion of the packet that it receives, and generate a hash value therefrom. If the receiving device determines that the generated hash value corresponds to the hash value received in the message packet, properties of the hash function that is used to generate the hash values enable it to conclude that the message packet was not tampered with during the transfer and that it originated from the one device. The system avoids the necessity of computation-intensive encryption and decryption for message packet transfer during a communication session.
Abstract:
A microprocessor in a computer system processes an instruction stream comprising instructions of a plurality of instruction types including an information retrieval instruction type. The microprocessor comprises a register set, a pending fault flag set, a functional unit, an information retrieval subsystem, and a control subsystem. The register set comprises a plurality of registers, each register for storing information. The pending fault flag set comprises a plurality of pending fault flags each associated with one of said registers, each pending fault flag having selected conditions including a pending fault condition and a no pending fault condition. The functional unit performs processing operations in response to information input thereto. The information retrieval subsystem initiates an information retrieval operation to retrieve of information from said information storage subsystem for storage in a register. The control subsystem controls the other elements of the microprocessor in response to the instructions in the instruction stream. In response to an instruction in the instruction stream of the information retrieval type, the control subsystem enables the information retrieval subsystem to initiate an information retrieval operation, and conditions the pending fault flag associated with said one of said registers to the pending fault condition in response to detection of a fault condition during the information retrieval operation. In response to an instruction in the instruction stream of another type, the control subsystem identifies a selected one of said registers as a source register, and enables information to be transferred from said source register to the functional unit for processing if the pending fault flag associated with said source register is in the no pending fault condition.