-
公开(公告)号：US11019303B2
公开(公告)日：2021-05-25
申请号：US16929990
申请日：2020-07-15
Inventor： Jae-Young Lee , Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim
IPC: H04N7/081 , H04H20/42 , H04L1/00 , H04L27/26 , H04N21/2343 , H04N21/2383 , H04N19/187 , H04N3/28 , H04N5/445 , H04N21/236
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, size information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.
-
公开(公告)号：US10979082B2
公开(公告)日：2021-04-13
申请号：US16559482
申请日：2019-09-03
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim , Jae-Young Lee , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
-
公开(公告)号：US10833708B2
公开(公告)日：2020-11-10
申请号：US16353423
申请日：2019-03-14
Inventor： Bo-Mi Lim , Sun-Hyoung Kwon , Sung-Ik Park , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
IPC: H03M13/27 , H04L1/00 , H04L12/863
Abstract: An apparatus and method for time interleaving corresponding to hybrid time interleaving mode are disclosed. An apparatus for time interleaving according to an embodiment of the present invention includes a twisted block interleaver configured to perform intra-subframe interleaving corresponding to time interleaving blocks; and a convolutional delay line configured to perform inter-subframe interleaving using an output of the twisted block interleaver.
-
公开(公告)号：US10819371B2
公开(公告)日：2020-10-27
申请号：US16506486
申请日：2019-07-09
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
-
公开(公告)号：US10804937B2
公开(公告)日：2020-10-13
申请号：US16395117
申请日：2019-04-25
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
-
Patent Agency Ranking
公开(公告)号：US10804936B2
公开(公告)日：2020-10-13
申请号：US16393788
申请日：2019-04-24
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
-
公开(公告)号：US10804931B2
公开(公告)日：2020-10-13
申请号：US16526678
申请日：2019-07-30
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
-
公开(公告)号：US10784894B2
公开(公告)日：2020-09-22
申请号：US16233596
申请日：2018-12-27
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
-
公开(公告)号：US10757362B2
公开(公告)日：2020-08-25
申请号：US16460773
申请日：2019-07-02
Inventor： Jae-Young Lee , Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim
IPC: H04N7/081 , H04H20/42 , H04L1/00 , H04L27/26 , H04N21/2343 , H04N21/2383 , H04N19/187 , H04N3/28 , H04N5/445 , H04N21/236
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, size information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.
-
公开(公告)号：US10756762B2
公开(公告)日：2020-08-25
申请号：US16100268
申请日：2018-08-10
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Nam-Ho Hur , Heung-Mook Kim
Abstract: Disclosed herein are a channel coding/decoding method in which a parity check matrix is transformed and an apparatus using the same. The channel-coding method includes loading a first exponent matrix, transforming the first exponent matrix into a second exponent matrix, creating a parity check matrix corresponding to a required block size using the second exponent matrix, and performing LDPC encoding using the parity check matrix.
-
-
-
-
-
-
-
-
-
Search Results
276
records
(took 0.023 seconds)
