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    Methods and arrangements for multi-layer in-vehicle network intrusion detection and characterization
    111.
    发明授权
    Methods and arrangements for multi-layer in-vehicle network intrusion detection and characterization 有权

    公开(公告)号：US11423145B2

    公开(公告)日：2022-08-23

    申请号：US16727565

    申请日：2019-12-26

    Applicant: Intel Corporation

    Inventor： Christopher N. Gutierrez ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang ,  Manoj Sastry ,  Liuyang L. Yang ,  Xiruo Liu

    IPC: G06F21/56

    Abstract: Logic may implement observation layer intrusion detection systems (IDSs) to combine observations by intrusion detectors and/or other intrusion detection systems. Logic may monitor one or more control units at one or more observation layers of an in-vehicle network, each of the one or more control units to perform a vehicle function. Logic may combine observations of the one or more control units at the one or more observation layers. Logic may determine, based on a combination of the observations, that one or more of the observations represent an intrusion. Logic may determine, based at least on the observations, characteristics of an attack, and to pass the characteristics of the attack information to a forensic logging system to log the attack or pass the characteristics of the attack to a recovery system for informed selection of recovery procedures. Logic may dynamically adjust a threshold for detection of suspicious activity.

    Hardware random forest: low latency, fully reconfigurable ensemble classification
    112.
    发明授权
    Hardware random forest: low latency, fully reconfigurable ensemble classification 有权

    公开(公告)号：US11409286B2

    公开(公告)日：2022-08-09

    申请号：US16718495

    申请日：2019-12-18

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Christopher Gutierrez ,  Shabbir Ahmed ,  Manoj Sastry ,  Liuyang Yang ,  Xiruo Liu

    IPC: G05D1/00 ,  G06N5/04 ,  G06F16/901 ,  G06K9/62

    Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.

    Efficient post-quantum anonymous attestation with signature-based join protocol and unlimited signatures
    113.
    发明授权
    Efficient post-quantum anonymous attestation with signature-based join protocol and unlimited signatures 有权

    公开(公告)号：US11362835B2

    公开(公告)日：2022-06-14

    申请号：US16455978

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Manoj Sastry ,  Rafael Misoczki

    IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

    Abstract: In one example an apparatus comprises a computer readable memory; and a signature module to generate a set of cryptographic keys for attestation of group member devices and a set of leaf nodes in a sub-tree of a Merkle tree corresponding to the set of cryptographic keys, forward the set of leaf nodes to a group manager device, receive, from the group manager device, a subset of intermediate nodes in the Merkle tree, the intermediate nodes being common to all available authentications paths through the Merkel tree for signatures originating in the sub-tree, and determine a cryptographic key that defines an authentication path through the Merkle tree, the authentication path comprising one or more nodes from the set of leaf nodes and one or more nodes from the intermediate nodes received from the group manager device. Other examples may be described.

    LOW-LATENCY DIGITAL SIGNATURE PROCESSING WITH SIDE-CHANNEL SECURITY
    119.
    发明申请
    LOW-LATENCY DIGITAL SIGNATURE PROCESSING WITH SIDE-CHANNEL SECURITY 有权

    公开(公告)号：US20220012334A1

    公开(公告)日：2022-01-13

    申请号：US17484870

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Andrea Basso ,  Manoj Sastry

    IPC: G06F21/55 ,  G06F7/72 ,  H04L9/32

    Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

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