公开(公告)号：US20220006630A1

公开(公告)日：2022-01-06

申请号：US17480360

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/30 ,  H04L9/32 ,  H04L9/08

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.

公开(公告)号：US12058261B2

公开(公告)日：2024-08-06

申请号：US17480360

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/30 ,  G06F17/14 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/3093 ,  H04L9/0869 ,  H04L9/3026 ,  H04L9/3247

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.

公开(公告)号：US20220012334A1

公开(公告)日：2022-01-13

申请号：US17484870

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Manoj Sastry

IPC: G06F21/55 ,  G06F7/72 ,  H04L9/32

Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

公开(公告)号：US11995184B2

公开(公告)日：2024-05-28

申请号：US17484870

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Manoj Sastry

IPC: G06F21/55 ,  G06F7/72 ,  G06F21/64 ,  G06F21/75 ,  H04L9/00 ,  H04L9/30 ,  H04L9/32

CPC classification number: G06F21/556 ,  G06F7/724 ,  G06F21/64 ,  G06F21/75 ,  H04L9/003 ,  H04L9/3093 ,  H04L9/3247 ,  G06F2207/7223

Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

公开(公告)号：US20230087297A1

公开(公告)日：2023-03-23

申请号：US17478624

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso

IPC: H04L9/32 ,  H04L9/30

Abstract: Modulus reduction for cryptography is described. An example of an apparatus includes multiplier circuitry to perform integer multiplication; and modulus reduction circuitry to perform modulus reduction based on a prime modulus, wherein the modulus reduction circuitry is to receive a product value, the product value resulting from multiplying a first n-bit value by a second n-bit value to generate the product value and perform modulus reduction to reduce the product value to a result within the prime modulus; and wherein the modulus reduction circuitry is based on shift and add operations.

公开(公告)号：US20220014363A1

公开(公告)日：2022-01-13

申请号：US17484820

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrea Basso ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/30 ,  G06F7/72

Abstract: Combined post-quantum security utilizing redefined polynomial calculation is described. An example of an apparatus includes a first circuit for key encapsulation operation; a second circuit for digital signature operation; and a NTT (Number Theoretic Transform) multiplier circuit, wherein the NTT multiplier circuit provides for polynomial multiplication for both the first circuit and the second circuit, wherein the apparatus is to remap coefficients of polynomials for the first circuit to a prime modulus for the second circuit, and perform polynomial multiplication for the first circuit utilizing the remapped coefficients of the polynomials for the first circuit.

公开(公告)号：US20220006611A1

公开(公告)日：2022-01-06

申请号：US17480413

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform an incomplete number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format, the plurality of compute nodes comprising at least a first NTT circuit comprising a single butterfly circuit to perform a series of butterfly calculations on input data; and a randomizing circuitry to randomize an order of the series of butterfly calculations.