公开(公告)号：US20060262610A1

公开(公告)日：2006-11-23

申请号：US11134450

申请日：2005-05-23

申请人： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  James Tschanz ,  Stephen Tang

发明人： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  James Tschanz ,  Stephen Tang

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C8/12

摘要： A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.

摘要翻译： 提供了一种降低集成存储器件功耗的方法和装置。 存储单元组可以通过相应的“睡眠”晶体管单独地进入“睡眠”模式。

公开(公告)号：US20060067109A1

公开(公告)日：2006-03-30

申请号：US10956195

申请日：2004-09-30

申请人： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  James Tschanz ,  Stephen Tang ,  Vivek De

发明人： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  James Tschanz ,  Stephen Tang ,  Vivek De

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C11/413

摘要： A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.

摘要翻译： 描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。

公开(公告)号：US06169419A

公开(公告)日：2001-01-02

申请号：US09151177

申请日：1998-09-10

申请人： Vivek K. De ,  Yibin Ye

发明人： Vivek K. De ,  Yibin Ye

IPC分类号： H03K190948

CPC分类号： H03K19/0016

摘要： Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.

摘要翻译： 使用晶体管堆叠效应减少内部电路块中的备用漏电流。 对于一个实施例，一种装置包括要耦合到包括多个逻辑门的电路块的备用泄漏减小电路。 备用泄漏降低电路在电路块的待机模式期间在多个逻辑门中的每一个处引起堆叠效应，通过关闭两个或更多个相同类型（n型或p型）的串联耦合晶体管 每个逻辑门。

公开(公告)号：US06653866B2

公开(公告)日：2003-11-25

申请号：US10277009

申请日：2002-10-21

申请人： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

发明人： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K19/01728

摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

公开(公告)号：US06275071B1

公开(公告)日：2001-08-14

申请号：US09474533

申请日：1999-12-29

申请人： Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

发明人： Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A domino logic circuit includes input connections to receive a clock signal and at least one input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising precharge circuitry, and a static stage that comprises discharge circuitry. In another embodiment, the domino logic circuit includes a dynamic stage comprising discharge circuitry, and a static stage that comprises precharge circuitry. Different configurations and transistor types have also been described. The circuitry can provide improved speed performance, or increase noise immunity.

摘要翻译： 多米诺逻辑电路包括用于接收时钟信号和至少一个输入数据信号的输入连接。 在一个实施例中，多米诺逻辑电路包括包括预充电电路的动态级和包括放电电路的静态级。 在另一个实施例中，多米诺骨牌逻辑电路包括包括放电电路的动态级和包括预充电电路的静态级。 还描述了不同的配置和晶体管类型。 该电路可以提供改进的速度性能，或提高抗噪声能力。

公开(公告)号：US06515513B2

公开(公告)日：2003-02-04

申请号：US09846604

申请日：2001-04-30

申请人： Yibin Ye ,  James W. Tschanz ,  Vivek K. De

发明人： Yibin Ye ,  James W. Tschanz ,  Vivek K. De

IPC分类号： H03K190175

CPC分类号： H03K19/0016

摘要： A method and apparatus for reducing leakage current in an integrated circuit includes a supply voltage line, a virtual supply voltage line, a ground voltage line, a virtual ground voltage line, a first logic circuit coupled to the ground voltage line and selectively coupled to the virtual supply voltage line, a second logic circuit coupled to the supply voltage line and selectively coupled to the virtual ground voltage line, and a switch circuit configured to control the selective coupling of the first logic circuit to the virtual supply line voltage and the second logic circuit to the virtual ground voltage line.

公开(公告)号：US06496040B1

公开(公告)日：2002-12-17

申请号：US09823633

申请日：2001-03-30

申请人： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

发明人： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

IPC分类号： H01L2500

CPC分类号： G06F17/5068

摘要： A stack device is provided to obtain a stack effect. The stack device includes at least first and second active components. The first and second active components have first and second device widths, respectively. The first and second device widths are then selected to provide a desired leakage current and gate delay time for the stack device. The selection includes adjusting the first and second device widths while keeping a sum of the device widths constant.

摘要翻译： 提供堆栈设备以获得堆栈效应。 堆叠装置至少包括第一和第二活动部件。 第一和第二有源部件分别具有第一和第二器件宽度。 然后选择第一和第二器件宽度以为堆叠器件提供期望的漏电流和栅极延迟时间。 该选择包括在保持设备宽度的总和恒定的同时调整第一和第二设备宽度。

公开(公告)号：US06329874B1

公开(公告)日：2001-12-11

申请号：US09151827

申请日：1998-09-11

申请人： Yibin Ye ,  Vivek K. De

发明人： Yibin Ye ,  Vivek K. De

IPC分类号： G05F110

CPC分类号： G05F3/205 ,  G11C2207/2227

摘要： Standby leakage reduction circuitry that uses boosted gate drive of a leakage control transistor during an active mode. A circuit block includes a first leakage control transistor coupled to receive a first supply voltage and coupled in series with an internal circuit block that performs a particular function. A gate drive circuit is included to apply a first boosted gate drive voltage to a gate of the first leakage control transistor during an active mode of the internal circuit block. The gate drive circuit furthers applies a standby gate voltage to the gate during a standby mode of the internal circuit block, the standby gate voltage to cause a gate to source voltage of the leakage control transistor to be reverse-biased.

摘要翻译： 待机泄漏降低电路，在活动模式期间使用泄漏控制晶体管的升压栅极驱动。 电路块包括耦合以接收第一电源电压并与执行特定功能的内部电路块串联耦合的第一泄漏控制晶体管。 包括栅极驱动电路以在内部电路块的有源模式期间将第一升压栅极驱动电压施加到第一泄漏控制晶体管的栅极。 栅极驱动电路在内部电路块的待机模式期间进一步向栅极施加备用栅极电压，使得使得漏极控制晶体管的栅极源极电压被反向偏置的待机栅极电压。

公开(公告)号：US06492837B1

公开(公告)日：2002-12-10

申请号：US09527344

申请日：2000-03-17

申请人： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

发明人： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K19/01728

摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

摘要翻译： 提供多米诺骨牌逻辑电路。 电路包括耦合在动态输出节点和高电压连接之间的n沟道时钟晶体管，时钟晶体管的栅极进一步耦合以接收反相时钟信号。 第一反相器具有连接到动态输出节点的输入。 具有连接到动态输出节点的输入的第二反相器包括静态CMOS电路级，其作为输出接收器电路，其输出是多米诺逻辑电路的输出。 N沟道电平保持器晶体管连接在动态输出节点和高压连接之间，电平保持晶体管的栅极连接到第一个反相器的输出端。 下拉电路连接在动态输出节点和低压连接之间。 输出预放电晶体管连接在静态CMOS电路的输出端和低电压连接端之间，并在其门口耦合并由时钟信号控制。

公开(公告)号：US06486706B2

公开(公告)日：2002-11-26

申请号：US09731515

申请日：2000-12-06

申请人： Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

发明人： Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A domino logic circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage, the output of which is the output of the domino logic circuit. A p-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. A pull-up circuit is connected between the static CMOS circuit output and the high voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.