Abstract:
A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.
Abstract:
An integrated search engine includes a hierarchical memory configured to support a plurality of multi-way trees of search keys. These multi-way trees, which share a common root node, support respective databases of search keys. The child pointers associated with search keys within the common root node may be allocated at a single key level of granularity, which means that each search key within the common root node may be associated with a pair of child pointers when each search key within the common root node is associated with a different multi-way tree of search keys.
Abstract:
A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.
Abstract:
A method and apparatus to reduce the number of rule entries used to implement ranging matching in a Content Addressable Memory (“CAM”) array. A first CAM entry is stored in a single CAM cell of an array of CAM cells. The first CAM entry is compared with a first key entry of the CAM array to generate a first comparison result. Each of multiple second CAM entries is stored in corresponding multiple CAM cells of the array of CAM cells. The multiple second CAM entries are compared with a second key entry to generate multiple second comparison results. A match signal is generated by the CAM array if the first key entry matches the first CAM entry and the second key entry matches one of the multiple second CAM entries.
Abstract:
A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.
Abstract:
An integrated circuit device for delivering power to a load includes a composite transistor and a composite schottky diode. The composite transistor is formed by a plurality of component transistors that have commonly coupled source terminals, commonly coupled drain terminals and commonly coupled gate terminals. The composite schottky diode is formed by a plurality of component schottky diodes that have anodes coupled in common and coupled to the source terminals of the plurality of component transistors, and for which drain terminals of the commonly coupled drain terminals constitute respective cathodes.
Abstract:
A content addressable memory (CAM) device includes a plurality of independently configurable CAM groups, each CAM group including a number of CAM rows and a programmable combinational logic circuit. Each CAM row includes a plurality of CAM cells coupled to a match line that generates a row match signal during a compare operation between a search key and data stored in the CAM row. The programmable combinational logic circuit logically combines the row match signals to generate a corresponding group match signal according to a respective one of a plurality of selectable logical operations selected by a corresponding function select signal.
Abstract:
An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.
Abstract:
A processing system includes a network processor and a CAM device having a re-entrant processor coupled to a CAM array. The re-entrant processor is configured to selectively modify an initial search key provided by the network processor by replacing portions of the initial search key with portions of one or more previous search keys and/or one or more previous results. The re-entrant processor is also configured to initiate a series of subsequent compare operations between new search keys and data stored in the CAM array without receiving additional instructions or search keys from the network processor.
Abstract:
Cost-based methods of exchanging/transferring intellectual property (IP) among parties are provided that include royalty rates and mark-up rates based on a common factor. The common factor of an embodiment includes the cost of a component material of a product. The IP includes at least one of technology, patents, and trade secrets. The methods include a first company that transfers IP to a second company. The first and second companies, in effecting the transfer, establish a royalty rate that is a first percentage of a cost of a component material of the products and a mark-up rate that is a second percentage of the cost of the component material.