Method and apparatus for shaping electronic pulses
    121.
    发明授权
    Method and apparatus for shaping electronic pulses 失效
    电子脉冲整形的方法和装置

    公开(公告)号:US07856570B1

    公开(公告)日:2010-12-21

    申请号:US11844836

    申请日:2007-08-24

    CPC classification number: H04L25/0278 H04L25/0288

    Abstract: A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.

    Abstract translation: 一种用于对具有双脉冲响应的电子脉冲进行整形的方法和系统。 输入节点接收初始电子脉冲并将电子脉冲分裂成第一路径和第二路径。 输出节点将第一路径和第二路径组合成输出路径,并且发送与输出阻抗匹配的成形电子脉冲。 以太网芯片产生两个脉冲,并分别沿着第一路径和第二路径发送脉冲。 功率组合器/分离器将沿着第一路径和第二路径的脉冲组合成输出路径,并且传输与输出阻抗匹配的成形电子脉冲。

    Integrated search engine devices having a plurality of multi-way trees of search keys therein that share a common root node
    122.
    发明授权
    Integrated search engine devices having a plurality of multi-way trees of search keys therein that share a common root node 失效
    具有共享公共根节点的多个搜索键的多路树的集成搜索引擎设备

    公开(公告)号:US07831626B1

    公开(公告)日:2010-11-09

    申请号:US11858441

    申请日:2007-09-20

    Applicant: Gary Depelteau

    Inventor: Gary Depelteau

    CPC classification number: G06F17/30327

    Abstract: An integrated search engine includes a hierarchical memory configured to support a plurality of multi-way trees of search keys. These multi-way trees, which share a common root node, support respective databases of search keys. The child pointers associated with search keys within the common root node may be allocated at a single key level of granularity, which means that each search key within the common root node may be associated with a pair of child pointers when each search key within the common root node is associated with a different multi-way tree of search keys.

    Abstract translation: 集成搜索引擎包括被配置为支持搜索关键字的多个多路树的分层存储器。 共享一个共同根节点的多路树支持相关的搜索关键数据库。 与公共根节点内的搜索关键字相关联的子指针可以以粒度的单个关键级别分配,这意味着当共同根节点内的每个搜索关键字在共同根目录内的每个搜索关键字时,共同根节点内的每个搜索关键字可以与一对子指针相关联 根节点与搜索关键字的不同多路树关联。

    Row expansion reduction by inversion for range representation in ternary content addressable memories
    123.
    发明授权
    Row expansion reduction by inversion for range representation in ternary content addressable memories 有权
    在三元内容可寻址存储器中的范围表示反转的行扩展减少

    公开(公告)号:US07814268B2

    公开(公告)日:2010-10-12

    申请号:US12072361

    申请日:2008-02-25

    CPC classification number: G11C15/00

    Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.

    Abstract translation: 实现与范围规则功能匹配的方法和电路。 存储第一条规则条目和第二条规则条目。 第一规则条目包括至少两个连续相同的比特。 第一个规则条目表示数值范围。 将二进制密钥的第一字段与第一规则条目进行比较,以确定第一字段的任何位是否不相同。 反转第一场和第一规则条目之间的比较的逻辑结果,以产生第一比较结果。 将二进制密钥的第二字段与第二规则条目进行比较以生成第二比较结果。 然后将第一比较结果与第二比较结果进行逻辑与运算,以确定二进制密钥是否落入由第一规则条目表示的数值范围内,并与第二规则条目匹配。

    Partial row expansion by logically combining range representation values in content addressable memory
    124.
    发明授权
    Partial row expansion by logically combining range representation values in content addressable memory 失效
    通过逻辑组合内容可寻址内存中的范围表示值进行部分行扩展

    公开(公告)号:US07814266B1

    公开(公告)日:2010-10-12

    申请号:US11219109

    申请日:2005-09-01

    CPC classification number: G11C15/04 H04L45/7453

    Abstract: A method and apparatus to reduce the number of rule entries used to implement ranging matching in a Content Addressable Memory (“CAM”) array. A first CAM entry is stored in a single CAM cell of an array of CAM cells. The first CAM entry is compared with a first key entry of the CAM array to generate a first comparison result. Each of multiple second CAM entries is stored in corresponding multiple CAM cells of the array of CAM cells. The multiple second CAM entries are compared with a second key entry to generate multiple second comparison results. A match signal is generated by the CAM array if the first key entry matches the first CAM entry and the second key entry matches one of the multiple second CAM entries.

    Abstract translation: 一种用于减少用于在内容可寻址存储器(“CAM”)阵列中实现测距匹配的规则条目数量的方法和装置。 第一CAM条目存储在CAM单元阵列的单个CAM单元中。 将第一CAM条目与CAM阵列的第一密钥条目进行比较以生成第一比较结果。 多个第二CAM条目中的每一个存储在CAM单元阵列的对应的多个CAM单元中。 将多个第二CAM条目与第二密钥条目进行比较以生成多个第二比较结果。 如果第一密钥条目与第一CAM条目匹配并且第二密钥条目匹配多个第二CAM条目中的一个,则由CAM阵列生成匹配信号。

    Content addressable memory (CAM) cell having column-wise conditional data pre-write
    125.
    发明授权
    Content addressable memory (CAM) cell having column-wise conditional data pre-write 失效
    具有列式条件数据预写的内容寻址存储器(CAM)单元

    公开(公告)号:US07813155B1

    公开(公告)日:2010-10-12

    申请号:US12288764

    申请日:2008-10-22

    CPC classification number: G11C15/04

    Abstract: A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.

    Abstract translation: 内容可寻址存储器(CAM)设备可以包括以行和列排列以形成多字节字的多个CAM单元。 每个CAM单元可以包括比较器电路和一个或多个数据存储电路。 每个比较器电路可以具有布置在匹配线和第一电压源节点之间的一个或多个电荷转移路径。 每个数据存储电路可以包括写入电路,其在一个或多个电荷传送路径与数据存储电路的数据存储节点之间提供可控阻抗路径。

    Transistor with spatially integrated schottky diode
    126.
    发明授权
    Transistor with spatially integrated schottky diode 有权
    具有空间积分肖特基二极管的晶体管

    公开(公告)号:US07808223B1

    公开(公告)日:2010-10-05

    申请号:US11746016

    申请日:2007-05-08

    CPC classification number: H02M3/1584 H01L21/823425 H01L27/0629

    Abstract: An integrated circuit device for delivering power to a load includes a composite transistor and a composite schottky diode. The composite transistor is formed by a plurality of component transistors that have commonly coupled source terminals, commonly coupled drain terminals and commonly coupled gate terminals. The composite schottky diode is formed by a plurality of component schottky diodes that have anodes coupled in common and coupled to the source terminals of the plurality of component transistors, and for which drain terminals of the commonly coupled drain terminals constitute respective cathodes.

    Abstract translation: 用于向负载输送功率的集成电路装置包括复合晶体管和复合肖特基二极管。 复合晶体管由具有共同耦合的源极端子,共同耦合的漏极端子和共同耦合的栅极端子的多个元件晶体管形成。 复合肖特基二极管由多个分量肖特基二极管形成,其具有共同耦合的阳极并耦合到多个元件晶体管的源极端子,并且共同耦合的漏极端子的漏极端子构成相应的阴极。

    Content addressable memory having programmable combinational logic circuits
    127.
    发明授权
    Content addressable memory having programmable combinational logic circuits 有权
    内容可寻址存储器,具有可编程组合逻辑电路

    公开(公告)号:US07787275B1

    公开(公告)日:2010-08-31

    申请号:US12341949

    申请日:2008-12-22

    CPC classification number: G11C15/00 G11C15/04 G11C15/046

    Abstract: A content addressable memory (CAM) device includes a plurality of independently configurable CAM groups, each CAM group including a number of CAM rows and a programmable combinational logic circuit. Each CAM row includes a plurality of CAM cells coupled to a match line that generates a row match signal during a compare operation between a search key and data stored in the CAM row. The programmable combinational logic circuit logically combines the row match signals to generate a corresponding group match signal according to a respective one of a plurality of selectable logical operations selected by a corresponding function select signal.

    Abstract translation: 内容可寻址存储器(CAM)设备包括多个独立配置的CAM组,每个CAM组包括多个CAM行和可编程组合逻辑电路。 每个CAM行包括耦合到匹配线的多个CAM单元,其在搜索关键字和存储在CAM行中的数据之间的比较操作期间生成行匹配信号。 可编程组合逻辑电路逻辑地组合行匹配信号,以根据由相应的功能选择信号选择的多个可选逻辑操作中的相应一个来产生对应的组匹配信号。

    Integrated circuit with reconfigurable inputs/outputs
    128.
    发明授权
    Integrated circuit with reconfigurable inputs/outputs 有权
    具有可重配置输入/输出的集成电路

    公开(公告)号:US07782084B1

    公开(公告)日:2010-08-24

    申请号:US12012672

    申请日:2008-02-04

    CPC classification number: H03K19/1732 H03K19/17744

    Abstract: An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.

    Abstract translation: 集成电路设备可以包括耦合到具有相对于彼此的预定物理顺序的多个信号路径的核心部分。 响应于配置信息,配置电路可以根据至少两个不同的物理顺序中的一个选择性地将每个信号路径连接到多个物理连接点中的对应的一个到IC设备。

    Re-entrant processing in a content addressable memory
    129.
    发明授权
    Re-entrant processing in a content addressable memory 失效
    在内容可寻址内存中进行重新处理

    公开(公告)号:US07694068B1

    公开(公告)日:2010-04-06

    申请号:US11298206

    申请日:2005-12-08

    Applicant: Andrew Rosman

    Inventor: Andrew Rosman

    CPC classification number: G11C15/00

    Abstract: A processing system includes a network processor and a CAM device having a re-entrant processor coupled to a CAM array. The re-entrant processor is configured to selectively modify an initial search key provided by the network processor by replacing portions of the initial search key with portions of one or more previous search keys and/or one or more previous results. The re-entrant processor is also configured to initiate a series of subsequent compare operations between new search keys and data stored in the CAM array without receiving additional instructions or search keys from the network processor.

    Abstract translation: 处理系统包括网络处理器和具有耦合到CAM阵列的重入处理器的CAM设备。 入侵者处理器被配置为通过用初始搜索关键字的一部分替换一个或多个先前的搜索关键字的部分和/或一个或多个先前的结果来选择性地修改由网络处理器提供的初始搜索关键字。 入侵处理器还被配置为在新的搜索关键字和存储在CAM阵列中的数据之间发起一系列随后的比较操作,而不从网络处理器接收附加的指令或搜索键。

    Cost-based technology and manufacturing exchange
    130.
    发明授权
    Cost-based technology and manufacturing exchange 失效
    基于成本的技术和制造交流

    公开(公告)号:US07685039B1

    公开(公告)日:2010-03-23

    申请号:US10810176

    申请日:2004-03-26

    CPC classification number: G06Q40/00

    Abstract: Cost-based methods of exchanging/transferring intellectual property (IP) among parties are provided that include royalty rates and mark-up rates based on a common factor. The common factor of an embodiment includes the cost of a component material of a product. The IP includes at least one of technology, patents, and trade secrets. The methods include a first company that transfers IP to a second company. The first and second companies, in effecting the transfer, establish a royalty rate that is a first percentage of a cost of a component material of the products and a mark-up rate that is a second percentage of the cost of the component material.

    Abstract translation: 提供了各方之间基于成本的交换/转让知识产权的方法,其中包括基于共同因素的专利费率和加价率。 实施例的共同因素包括产品的部件材料的成本。 IP包括技术,专利和商业秘密中的至少一项。 这些方法包括将IP转移给第二家公司的第一家公司。 在实施转让的第一和第二家公司中,建立了专利费率,这是产品成分材料成本的第一百分比,标价率是零部件材料成本的二分之一。

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