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    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12095461B2

    公开(公告)日：2024-09-17

    申请号：US18054978

    申请日：2022-11-14

    申请人： RENESAS ELECTRONICS CORPORATION

    发明人： Daisuke Moriyama

    IPC分类号： H03K19/17 ,  H03K19/0185 ,  H03K19/17736 ,  H03K19/17768

    CPC分类号： H03K19/17768 ,  H03K19/018564 ,  H03K19/17744

    摘要： A semiconductor device includes: an arithmetic circuit that repeats an operation related to a cryptographic processing for the predetermined number of rounds; a holding circuit that holds data related to the number of rounds of an operation of the arithmetic circuit; a judgement circuit that determines whether the number of rounds is the predetermined number of rounds; and an output buffer circuit that outputs the arithmetic result data of the arithmetic circuit when the judgement circuit determines that the number of rounds is the predetermined number. It is configured to duplicate the holding circuit, and not to output the arithmetic result data when two outputs of the duplicated holding circuit are not matched.

    PROGRAMMABLE STREAM SWITCHES AND FUNCTIONAL SAFETY CIRCUITS IN INTEGRATED CIRCUITS
    3.
    发明公开
    PROGRAMMABLE STREAM SWITCHES AND FUNCTIONAL SAFETY CIRCUITS IN INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20240195418A1

    公开(公告)日：2024-06-13

    申请号：US18062828

    申请日：2022-12-07

    申请人： Xilinx, Inc.

    发明人： Karl Henrik Goran Bilski

    IPC分类号： H03K19/0175 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/17768

    CPC分类号： H03K19/017581 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/17768

    摘要： An integrated circuit (IC) may include a plurality of compute tiles in a data processing array. Each compute tile is configured to perform a data processing function. The IC may include a plurality of interface tiles in the data processing array. The plurality of interface tiles are communicatively linked to the plurality of compute tiles. The IC may include a plurality of programmable stream switches disposed in the plurality of compute tiles and the plurality of interface tiles. The IC may include a functional safety circuit. The functional safety circuit is connected to a selected programmable stream switch of the plurality of programmable stream switches. The functional safety circuit is configured to perform a functional safety function on a plurality of data streams routed to the functional safety circuit from the selected programmable stream switch.

    Configuration bit using RRAM
    6.
    发明授权
    Configuration bit using RRAM 有权

    公开(公告)号：US11973500B2

    公开(公告)日：2024-04-30

    申请号：US17696473

    申请日：2022-03-16

    申请人： Crossbar, Inc.

    发明人： Sang Nguyen ,  Cung Vu ,  Hagop Nazarian

    IPC分类号： H03K19/177 ,  G11C13/00 ,  H03K19/17736 ,  H03K19/17758 ,  H03K19/1776

    CPC分类号： H03K19/1776 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/0097 ,  H03K19/17744 ,  H03K19/17758

    摘要： A field programmable gate array (FPGA) utilizing resistive switching memory technology is described. The FPGA can comprise a switching block interconnect having a set of signal input lines and a set of signal output lines. Respective intersections of the signal input lines and signal output lines can have two resistive switching memory cells, a current differential latch, and a switching transistor (also referred to as a pass gate transistor) arranged in a circuit. Resistance states of the resistive switching memory cells can be programmed to control an output voltage state of the current differential latch. The output voltage state is latched into the current differential latch which can drive a gate of the switching transistor to activate or deactivate the switching transistor, which in turn activates or deactivates an intersection of the FPGA.

    Flash memory emulation
    9.
    发明授权
    Flash memory emulation 有权

    公开(公告)号：US11874768B1

    公开(公告)日：2024-01-16

    申请号：US16684477

    申请日：2019-11-14

    申请人： XILINX, INC.

    发明人： Daniel Steger

    IPC分类号： G06F12/02 ,  G06F12/10 ,  H03K19/177 ,  H03K19/1776 ,  H03K19/17736

    CPC分类号： G06F12/0246 ,  G06F12/10 ,  H03K19/1776 ,  H03K19/17744

    摘要： Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.

    CHAINED PROGRAMMABLE DELAY ELEMENTS
    10.
    发明公开
    CHAINED PROGRAMMABLE DELAY ELEMENTS 审中-公开

    公开(公告)号：US20230378947A1

    公开(公告)日：2023-11-23

    申请号：US18228502

    申请日：2023-07-31

    申请人： EFINIX, INC.

    发明人： Marcel Gort

    IPC分类号： H03K5/133 ,  H03K19/17736

    CPC分类号： H03K5/133 ,  H03K19/17744 ,  H03K19/1774 ,  H03K2005/00019

    摘要： Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.