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公开(公告)号：US20190296951A1
公开(公告)日：2019-09-26
申请号：US16357735
申请日：2019-03-19
Inventor： Sun-Hyoung KWON , Sung-Ik PARK , Jae-Young LEE , Bo-Mi LIM , Heung-Mook KIM
Abstract: Disclosed herein are an apparatus for analyzing a transmitter identification (TxID) signal and a method using the apparatus. The apparatus for analyzing the TxID signal includes a demodulator for decoding the bootstrap of a received signal; a cancellation unit for performing a host signal cancellation process for the received signal, thereby generating a host-signal-cancelled received signal; a correlator for calculating a correlation value between a signal corresponding to the host-signal-cancelled received signal and a signal corresponding to a TxID sequence; and a TxID profile analyzer for generating information about a channel between a transmitter corresponding to the TxID signal and a receiver using the correlation value.
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公开(公告)号：US20190268024A1
公开(公告)日：2019-08-29
申请号：US16405719
申请日：2019-05-07
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US20190260395A1
公开(公告)日：2019-08-22
申请号：US16400988
申请日：2019-05-01
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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124.发明申请公开(公告)号：US20190260389A1
公开(公告)日：2019-08-22
申请号：US16400934
申请日：2019-05-01
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US20190253082A1
公开(公告)日：2019-08-15
申请号：US16395117
申请日：2019-04-25
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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Patent Agency Ranking
126.发明申请公开(公告)号：US20190230199A1
公开(公告)日：2019-07-25
申请号：US16313790
申请日：2017-07-05
Inventor： Bo-Mi LIM , Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC: H04L29/08
Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.
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公开(公告)号：US20190229754A1
公开(公告)日：2019-07-25
申请号：US16369742
申请日：2019-03-29
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , G06F11/1004 , G06F11/1076 , G11B20/1806 , G11B20/1809 , G11B2020/185 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/27 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
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公开(公告)号：US20190222231A1
公开(公告)日：2019-07-18
申请号：US16353423
申请日：2019-03-14
Inventor： Bo-Mi LIM , Sun-Hyoung KWON , Sung-Ik PARK , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2732 , H04L1/0043 , H04L1/0048 , H04L1/0057 , H04L1/0059 , H04L1/007 , H04L1/0071 , H04L47/6245
Abstract: An apparatus and method for time interleaving corresponding to hybrid time interleaving mode are disclosed. An apparatus for time interleaving according to an embodiment of the present invention includes a twisted block interleaver configured to perform intra-subframe interleaving corresponding to time interleaving blocks; and a convolutional delay line configured to perform inter-subframe interleaving using an output of the twisted block interleaver.
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129.发明申请公开(公告)号：US20190215009A1
公开(公告)日：2019-07-11
申请号：US16353378
申请日：2019-03-14
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
Abstract: A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.
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公开(公告)号：US20190052287A1
公开(公告)日：2019-02-14
申请号：US16100268
申请日：2018-08-10
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Nam-Ho HUR , Heung-Mook KIM
CPC classification number: H03M13/116 , H03M13/1105 , H03M13/118 , H03M13/6516 , H04L1/0057
Abstract: Disclosed herein are a channel coding/decoding method in which a parity check matrix is transformed and an apparatus using the same. The channel-coding method includes loading a first exponent matrix, transforming the first exponent matrix into a second exponent matrix, creating a parity check matrix corresponding to a required block size using the second exponent matrix, and performing LDPC encoding using the parity check matrix.
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